Clock distribution networks for 3-D ictegrated Circuits. - Vasilis F. Pavlidis; Ioannis Savidis; Eby G. Friedman (CICC, 2008)

Electrical modeling and characterization of 3-D vias. - Ioannis Savidis; Eby G. Friedman (ISCAS, 2008)

An intra-chip free-space optical interconnect. - Jing Xue; Alok Garg; Berkehan Ciftcioglu; Jianyun Hu; Shang Wang; Ioannis Savidis; Manish Jain; Rebecca Berman; Peng Liu 016; Michael C. Huang 001; Hui Wu 007; Eby G. Friedman; et al. (ISCA, 2010)

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits. - Ioannis Savidis; Syed M. Alam; Ankur Jain; Scott Pozder; Robert E. Jones; Ritwik Chatterjee (Microelectron. J., 2010)

Clock distribution models of 3-D integrated systems. - Ioannis Savidis; Vasilis F. Pavlidis; Eby G. Friedman (ISCAS, 2011)

Thermal analysis of oxide-confined VCSEL arrays. - Jinhui Wang; Ioannis Savidis; Eby G. Friedman (Microelectron. J., 2011)

Clock Distribution Networks in 3-D Integrated Systems. - Vasilis F. Pavlidis; Ioannis Savidis; Eby G. Friedman (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Power Noise in TSV-Based 3-D Integrated Circuits. - Ioannis Savidis; Selçuk Köse; Eby G. Friedman (IEEE J. Solid State Circuits, 2013)

Thermal conduction path analysis in 3-D ICs. - Boris Vaisband; Ioannis Savidis; Eby G. Friedman (ISCAS, 2014)

Run-time voltage detection circuit for 3-D IC power delivery. - Divya Pathak; Ioannis Savidis (SoCC, 2014)

ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling. - Mohammad Khavari Tavana; Mohammad Hossein Hajkazemi; Divya Pathak; Ioannis Savidis; Houman Homayoun (DAC, 2015)

Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping. - Mohammad Khavari Tavana; Divya Pathak; Mohammad Hossein Hajkazemi; Maria Malik; Ioannis Savidis; Houman Homayoun (ICCD, 2015)

Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits. - Ioannis Savidis; Boris Vaisband; Eby G. Friedman (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Reduced Overhead Gate Level Logic Encryption. - Kyle Juretus; Ioannis Savidis (ACM Great Lakes Symposium on VLSI, 2016)

Load Balanced On-Chip Power Delivery for Average Current Demand. - Divya Pathak; Mohammad Hossein Hajkazemi; Mohammad Khavari Tavana; Houman Homayoun; Ioannis Savidis (ACM Great Lakes Symposium on VLSI, 2016)

Robust near-threshold inverter with improved performance for ultra-low power applications. - Md Shazzad Hossain; Ioannis Savidis (ISCAS, 2016)

Reducing logic encryption overhead through gate level key insertion. - Kyle Juretus; Ioannis Savidis (ISCAS, 2016)

Energy efficient on-chip power delivery with run-time voltage regulator clustering. - Divya Pathak; Mohammad Hossein Hajkazemi; Mohammad Khavari Tavana; Houman Homayoun; Ioannis Savidis (ISCAS, 2016)

A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures. - Kostas Siozios; Ioannis Savidis; Dimitrios Soudris (SAMOS, 2016)

Heterogeneous 3-D circuits: Integrating free-space optics with CMOS. - Ioannis Savidis; Berkehan Ciftcioglu; Jie Xu; Jianyun Hu; Manish Jain; Rebecca Berman; Jing Xue; Peng Liu 016; Duncan Moore; Gary Wicks; Michael C. Huang 001; Hui Wu 007; et al. (Microelectron. J., 2016)

Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery. - Divya Pathak; Houman Homayoun; Ioannis Savidis (ACM Great Lakes Symposium on VLSI, 2017)

Parameter biasing obfuscation for analog IP protection. - Vaibhav Venugopal Rao; Ioannis Savidis (HOST, 2017)

Physical gate based preamble obfuscation for securing wireless communication. - James Chacko; Kyle Juretus; Marko Jacovic; Cem Sahin; Nagarajan Kandasamy; Ioannis Savidis; Kapil R. Dandekar (ICNC, 2017)

Protecting analog circuits with parameter biasing obfuscation. - Vaibhav Venugopal Rao; Ioannis Savidis (LATS, 2017)

Bi-directional input/output circuits with integrated level shifters for near-threshold computing. - Md Shazzad Hossain; Ioannis Savidis (MWSCAS, 2017)

Clock tree synthesis for heterogeneous 3-D integrated circuits. - Isuru Daulagala; Ioannis Savidis (SLIP, 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery. - Divya Pathak; Houman Homayoun; Ioannis Savidis (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security. - Kyle Juretus; Ioannis Savidis (APCCAS, 2018)

Transistor Sizing for Parameter Obfuscation of Analog Circuits Using Satisfiability Modulo Theory. - Vaibhav Venugopal Rao; Ioannis Savidis (APCCAS, 2018)

Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning. - Hossein Sayadi; Divya Pathak; Ioannis Savidis; Houman Homayoun (ASP-DAC, 2018)

Securing the Systems of the Future - Techniques for a Shifting Attack Space. - Ioannis Savidis; Swarup Bhunia; Gang Qu 001; Matthew J. Casto; Jeremy Muldavin (ACM Great Lakes Symposium on VLSI, 2018)

Multi-Voltage Domain Power Distribution Network for Optimized Ultra-Low Voltage Clock Delivery. - Md Shazzad Hossain; Ioannis Savidis (IGSC, 2018)

Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures. - David Werner; Kyle Juretus; Ioannis Savidis; Mark Hempstead (ICCD, 2018)

Noise Constrained Optimum Selection of Supply Voltage for IoT Applications. - Md Shazzad Hossain; Ioannis Savidis (ISCAS, 2018)

Time Domain Sequential Locking for Increased Security. - Kyle Juretus; Ioannis Savidis (ISCAS, 2018)

On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors. - Divya Pathak; Ioannis Savidis (IEEE Trans. Very Large Scale Integr. Syst., 2018)

ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling. - Mohammad Khavari Tavana; Mohammad Hossein Hajkazemi; Divya Pathak; Ioannis Savidis; Houman Homayoun (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies. - Kyle Juretus; Vaibhav Venugopal Rao; Ioannis Savidis (ACM Great Lakes Symposium on VLSI, 2019)

Applying Swarm Intelligence to Distributed On-Chip Power Management. - Divya Pathak; Ioannis Savidis (ICCD, 2019)

Reusing Leakage Current for Improved Energy Efficiency of Multi-Voltage Systems. - Md Shazzad Hossain; Ioannis Savidis (ISCAS, 2019)

Increasing the SAT Attack Resiliency of In-Cone Logic Locking. - Kyle Juretus; Ioannis Savidis (ISCAS, 2019)

Mesh Based Obfuscation of Analog Circuit Properties. - Vaibhav Venugopal Rao; Ioannis Savidis (ISCAS, 2019)

Robust Low Power Clock Synchronization for Multi-Die Systems. - Ragh Kuttappa; Baris Taskin; Scott Lerner; Vasil Pano; Ioannis Savidis (ISLPED, 2019)

Securing Wireless Communication via Hardware-Based Packet Obfuscation. - James Chacko; Kyle Juretus; Marko Jacovic; Cem Sahin; Nagarajan Kandasamy; Ioannis Savidis; Kapil R. Dandekar (J. Hardw. Syst. Secur., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Reducing Logic Locking Key Leakage through the Scan Chain. - Kyle Juretus; Ioannis Savidis (ISCAS, 2020)

Modeling SAT-Attack Search Complexity. - Saran Phatharodom; Nagarajan Kandasamy; Ioannis Savidis (ISCAS, 2020)

Security Vulnerabilities of Obfuscated Analog Circuits. - Vaibhav Venugopal Rao; Kyle Juretus; Ioannis Savidis (ISCAS, 2020)

Dynamic idle core management and leakage current reuse in MPSoC platforms. - Md Shazzad Hossain; Ioannis Savidis (ISLPED, 2020)

CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing. - Zhengfeng Wu; Ioannis Savidis (MLCAD, 2020)

Physical Layer Encryption for Wireless OFDM Communication Systems. - Marko Jacovic; Kyle Juretus; Nagarajan Kandasamy; Ioannis Savidis; Kapil R. Dandekar (J. Hardw. Syst. Secur., 2020)

Recycling of unused leakage current for energy efficient multi-voltage systems. - Md Shazzad Hossain; Ioannis Savidis (Microelectron. J., 2020)

Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing. - Md Shazzad Hossain; Ioannis Savidis (Microelectron. J., 2020)

Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack. - Kyle Juretus; Ioannis Savidis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Energy Efficient Computing with Heterogeneous DNN Accelerators. - Md Shazzad Hossain; Ioannis Savidis (AICAS, 2021)

A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop. - Sayed Aresh Beheshti-Shirazi; Ashkan Vakil; Sai Manoj P. D.; Ioannis Savidis; Houman Homayoun; Avesta Sasan (ACM Great Lakes Symposium on VLSI, 2021)

SAT-attack Resilience Measure for Access Restricted Circuits. - Saran Phatharodom; Avesta Sasan; Ioannis Savidis (ACM Great Lakes Symposium on VLSI, 2021)

Reconfigurable Array for Analog Applications. - Ziyi Chen; Ioannis Savidis (ICCD, 2021)

Variation-aware Analog Circuit Sizing with Classifier Chains. - Zhengfeng Wu; Ioannis Savidis (MLCAD, 2021)

Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators. - Md Shazzad Hossain; Ioannis Savidis (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Synthesis of Hidden State Transitions for Sequential Logic Locking. - Kyle Juretus; Ioannis Savidis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking. - Kyle Juretus; Ioannis Savidis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Performance and Security Analysis of Parameter-Obfuscated Analog Circuits. - Vaibhav Venugopal Rao; Ioannis Savidis (IEEE Trans. Very Large Scale Integr. Syst., 2021)

RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis. - Tanmoy Chowdhury; Ashkan Vakil; Banafsheh Saber Latibari; Sayed Aresh Beheshti-Shirazi; Ali Mirzaeian; Xiaojie Guo 002; Sai Manoj P. D.; Houman Homayoun; Ioannis Savidis; Liang Zhao 002; Avesta Sasan (ACM Great Lakes Symposium on VLSI, 2022)

Practical Performance of Analog Attack Techniques. - Vaibhav Venugopal Rao; Kyle Juretus; Ioannis Savidis (HOST, 2022)

Reconfigurable Analog Array for Hardware Security. - Ziyi Chen; Ioannis Savidis (ISCAS, 2022)

Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking. - Pratik Shrestha; Ioannis Savidis (ISCAS, 2022)

Transfer Learning for Reuse of Analog Circuit Sizing Models Across Technology Nodes. - Zhengfeng Wu; Ioannis Savidis (ISCAS, 2022)

Adaptive-Gravity: A Defense Against Adversarial Samples. - Ali Mirzaeian; Zhi Tian; Sai Manoj P. D.; Banafsheh S. Latibari; Ioannis Savidis; Houman Homayoun; Avesta Sasan (ISQED, 2022)

Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits. - Vaibhav Venugopal Rao; Avesta Sasan; Ioannis Savidis (ISQED, 2022)

Graph Representation Learning for Gate Arrival Time Prediction. - Pratik Shrestha; Saran Phatharodom; Ioannis Savidis (MLCAD, 2022)

Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural Networks. - Zhengfeng Wu; Ioannis Savidis (MLCAD, 2022)

A Power Side-Channel Attack on Flash ADC. - Ziyi Chen; Ioannis Savidis (ISCAS, 2023)

Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect. - Pratik Shrestha; Ioannis Savidis (ISCAS, 2023)

Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies. - Zhengfeng Wu; Ioannis Savidis (ISCAS, 2023)

Hybrid Utilization of Subgraph Isomorphism and Relational Graph Convolutional Networks for Analog Functional Grouping Annotation. - Zhengfeng Wu; Isabel Song; Ioannis Savidis (MLCAD, 2023)

Hidden Costs of Analog Deobfuscation Attacks. - Vaibhav Venugopal Rao; Kyle Juretus; Ioannis Savidis (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Harnessing Heterogeneity for Targeted Attacks on 3-D ICs. - Alec Aversa; Ioannis Savidis (ACM Great Lakes Symposium on VLSI, 2024)

EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design Automation. - Pratik Shrestha; Alec Aversa; Saran Phatharodom; Ioannis Savidis (ACM Great Lakes Symposium on VLSI, 2024)

Block Configuration Algorithms for a Reconfigurable Analog Array. - Ziyi Chen; Ioannis Savidis (ISCAS, 2024)

DNA: DC Nodal Analysis Attack for Analog Circuits. - Vaibhav Venugopal Rao; Kyle Juretus; Ioannis Savidis (ISCAS, 2024)

Edge-weighted Graph Neural Networks for Post-placement Interconnect Capacitance Estimation of Analog Circuits. - Zhengfeng Wu; Ioannis Savidis (ISCAS, 2024)

EDA-ML: Graph Representation Learning Framework for Digital IC Design Automation. - Pratik Shrestha; Ioannis Savidis (ISQED, 2024)

Comparative Analysis of Graph Isomorphism and Graph Neural Networks for Analog Hierarchy Labeling. - Zhengfeng Wu; Ioannis Savidis (ISQED, 2024)

TARN: Trust Aware Routing to Enhance Security in 3D Network-on-Chips. - Hasin Ishraq Reefat; Alec Aversa; Ioannis Savidis; Naghmeh Karimi (DATE, 2025)

Avoiding Malicious Nodes of a 3-D NoC with Security-Aware Priority-Based Routing. - Alec Aversa; Hasin Ishraq Reefat; Naghmeh Karimi; Ioannis Savidis (ACM Great Lakes Symposium on VLSI, 2025)

Differentiable Graph Neural Networks for Wirelength Estimation. - Zhengfeng Wu; Pratik Shrestha; Saran Phatharodom; Ioannis Savidis (ISCAS, 2025)

Deep Representation Learning for Electronic Design Automation. - Pratik Shrestha; Saran Phatharodom; Alec Aversa; David Blankenship; Zhengfeng Wu; Ioannis Savidis (CoRR, 2025)

Emerging ML-AI Techniques for Analog and RF EDA. - Zhengfeng Wu; Ziyi Chen; Nnaemeka Achebe; Vaibhav Venugopal Rao; Pratik Shrestha; Ioannis Savidis (CoRR, 2025)

Synthesis of Analog and Mixed-Signal Circuits on a Programmable Array. - Ziyi Chen; Ioannis Savidis (IEEE Trans. Very Large Scale Integr. Syst., 2025)