Hardware primitives for the synthesis of multithreaded elastic systems. - Giorgos Dimitrakopoulos; I. Seitanidis; Anastasios Psarras; K. Tsiouris; Pavlos M. Mattheakis; Jordi Cortadella (DATE, 2014)

ElastiStore: An elastic buffer architecture for Network-on-Chip routers. - I. Seitanidis; Anastasios Psarras; Giorgos Dimitrakopoulos; Chrysostomos Nicopoulos (DATE, 2014)

ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture. - I. Seitanidis; Anastasios Psarras; Emmanouil Kalligeros; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (NOCS, 2014)

PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation. - Anastasios Psarras; I. Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (DATE, 2015)

ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip. - Ioannis Seitanidis; Anastasios Psarras; Kypros Chrysanthou; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Powermax: an automated methodology for generating peak-power traffic in networks-on-chip. - Ioannis Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (NOCS, 2016)

ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing. - Anastasios Psarras; Ioannis Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Computers, 2016)

PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels. - Anastasios Psarras; Junghee Lee; Ioannis Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. - Ioannis Seitanidis; Giorgos Dimitrakopoulos; Pavlos M. Mattheakis; Laurent Masse-Navette; David G. Chinnery (DAC, 2017)

Timing-Driven and Placement-Aware Multibit Register Composition. - Ioannis Seitanidis; Giorgos Dimitrakopoulos; Pavlos M. Mattheakis; Laurent Masse-Navette; David G. Chinnery (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Automatic Generation of Peak-Power Traffic for Networks-on-Chip. - Ioannis Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering. - Dimitrios Mangiras; Apostolos Stefanidis; Ioannis Seitanidis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)