A syndrome-based LDPC decoder with very low error floor. - Ioannis Tsatsaragkos; Nikos Kanistras; Vassilis Paliouras (DSP, 2011)

Multiple LDPC decoder of very low bit-error rate. - Ioannis Tsatsaragkos; Nikos Kanistras; Vassilis Paliouras (DSP, 2011)

Digital baseband challenges for a 60GHz gigabit link. - Nikos Kanistras; Ioannis Tsatsaragkos; Ahmed Mahdi; Konstantina Karagianni; Vassilis Paliouras; Fotios Gioulekas; E. Lalos; Kostas Adaos; Michael K. Birbas; Panos Karaivazoglou; M. V. Koziotis; M. Perakis (ICECS, 2011)

A flexible layered LDPC decoder. - Ioannis Tsatsaragkos; Vassilis Paliouras (ISWCS, 2011)

Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs. - Ahmed Mahdi; Panagiotis Sakellariou; Nikos Kanistras; Ioannis Tsatsaragkos; Vassilis Paliouras (ICECS, 2012)

An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems. - Panagiotis Sakellariou; Ioannis Tsatsaragkos; Nikos Kanistras; Ahmed Mahdi; Vassilis Paliouras (ICSAMOS, 2012)

Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding. - Nikos Kanistras; Ioannis Tsatsaragkos; Vassilis Paliouras (SiPS, 2012)

Error Floor Compensation for LDPC Codes Using Concatenated Schemes. - G. Spourlis; Ioannis Tsatsaragkos; Nikos Kanistras; Vassilis Paliouras (SiPS, 2012)

Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation. - Ioannis Tsatsaragkos; Vassilis Paliouras (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications. - Ioannis Tsatsaragkos; Vassilis Paliouras (IEEE Trans. Very Large Scale Integr. Syst., 2018)