Analyzing the Resilience to SEUs of an Image Data Compression Core in a COTS SRAM FPGA. - Ioannis Tsounis; Antonis Tsigkanos; Vasileios Vlagkoulis; Mihalis Psarakis; Nektarios Kranitis; Antonis M. Paschalis (AHS, 2019)

Analyzing the Impact of Approximate Adders on the Reliability of FPGA Accelerators. - Ioannis Tsounis; Athanasios Papadimitriou; Mihalis Psarakis (ETS, 2021)

Detecting Hardware Faults in Approximate Adders via Minimum Redundancy. - Ioannis Tsounis; Dimitris Agiakatsikas; Mihalis Psarakis (IOLTS, 2023)

A Methodology for Fault-tolerant Pareto-optimal Approximate Designs of FPGA-based Accelerators. - Ioannis Tsounis; Dimitris Agiakatsikas; Mihalis Psarakis (ACM Trans. Embed. Comput. Syst., 2023)

An Effective TMR Approach for Low-Latency Configurable-Accuracy Adders. - Ioannis Tsounis; Dimitris Agiakatsikas; Mihalis Psarakis (DFT, 2024)