A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages. - Chi-Hang Chan; Yan Zhu 001; Iok-Meng Ho; Wai-Hong Zhang; Chon-Lam Lio; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2016)

16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. - Chi-Hang Chan; Yan Zhu 001; Iok-Meng Ho; Wai-Hong Zhang; Seng-Pan U; Rui Paulo Martins (ISSCC, 2017)

60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. - Chi-Hang Chan; Yan Zhu 001; Cheng Li 010; Wai-Hong Zhang; Iok-Meng Ho; Lai Wei; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)