RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints. - Christos Georgakidis; Iordanis Lilitsis; Georgios Stanimeropoulos; Christos P. Sotiriou (DFT, 2021)

Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows. - Nikolaos Blias; Iordanis Lilitsis; Stavros Simoglou; Evangelos Bakas; Christos P. Sotiriou (VLSI-SoC, 2022)

Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops. - Nikolaos Chatzivangelis; Dimitris Valiantzas; Christos P. Sotiriou; Iordanis Lilitsis (VLSI-SoC, 2022)

Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis. - Christos Georgakidis; Dimitris Valiantzas; Stavros Simoglou; Iordanis Lilitsis; Nikolaos Chatzivangelis; Ilias Golfos; Marko S. Andjelkovic; Christos P. Sotiriou; Milos Krstic (DFT, 2023)

Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model. - Stavros Simoglou; Iordanis Lilitsis; Nikolaos Blias; Christos P. Sotiriou (ISQED, 2024)