Low-voltage CMOS syllabic-companding log domain filter. - Ippei Akita; Kazuyuki Wada; Yoshiaki Tadokoro (ISCAS, 2006)

Simplified Low-Voltage CMOS Syllabic Companding Log Domain Filter. - Ippei Akita; Kazuyuki Wada; Yoshiaki Tadokoro (ISCAS, 2007)

Synthesis Method of All Low-Voltage CMOS Instantaneous-Companding Log Domain Integrators. - Ippei Akita; Kazuyuki Wada; Yoshiaki Tadokoro (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A 0.8-V Syllabic-Companding Log Domain Filter with 78-dB Dynamic Range in 0.35-µm CMOS. - Ippei Akita; Kazuyuki Wada; Yoshiaki Tadokoro (IEICE Trans. Electron., 2008)

A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-µm CMOS. - Ippei Akita; Kazuyuki Wada; Yoshiaki Tadokoro (IEEE J. Solid State Circuits, 2009)

A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier. - Ippei Akita; Masanori Furuta; Junya Matsuno; Tetsuro Itakura (A-SSCC, 2011)

A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS. - Ippei Akita; Yuta Tsubouchi; Tetsuro Itakura; Michihiko Nishigaki; Hiroshi Uemura; Hideto Furuyama; Hideki Shibata (ESSCIRC, 2011)

Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch. - Ippei Akita; Tetsuro Itakura; Kei Shiraishi (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 0.06mm2 14nV/√Hz chopper instrumentation amplifier with automatic differential-pair matching. - Ippei Akita; Makoto Ishida (ISSCC, 2013)

A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS. - Masanori Furuta; Ippei Akita; Junya Matsuno; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A current noise reduction technique in chopper instrumentation amplifier for high-impedance sensors. - Ippei Akita; Makoto Ishida (IEICE Electron. Express, 2015)

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems. - Kenji Okabe; Horagodage Prabhath Jeewan; Shota Yamagiwa; Takeshi Kawano; Makoto Ishida; Ippei Akita (Sensors, 2015)

A robust and low-power synchronization technique of coarse-and-fine conversion parts in ring-oscillator-based time-to-digital converters. - Takayuki Okazawa; Ippei Akita (ICECS, 2017)

A 181NW 970µG✓HZ Accelerometer Analog Front-End Employing Feedforward Noise Reduction Technique. - Ippei Akita; Takayuki Okazawa; Yoshihiko Kurui; Akira Fujimoto; Takashi Asano 002 (VLSI Circuits, 2018)

A Dynamic Latched Comparator Using Area-Efficient Stochastic Offset Voltage Detection Technique. - Takayuki Okazawa; Ippei Akita (IEICE Trans. Electron., 2018)

A Time-Domain Analog Spatial Compressed Sensing Encoder for Multi-Channel Neural Recording. - Takayuki Okazawa; Ippei Akita (Sensors, 2018)

An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. - Yuji Yano; Seiya Yoshida; Shintaro Izumi; Hiroshi Kawaguchi 001; Tetsuya Hirose; Masaya Miyahara; Teruki Someya; Kenichi Okada 001; Ippei Akita; Yoshihiko Kurui; Hideyuki Tomizawa; Masahiko Yoshimoto (A-SSCC, 2019)

A 0.338 cm3, Artifact-Free, 64-Contact Neuromodulation Platform for Simultaneous Stimulation and Sensing. - Dejan Rozgic; Vahagn Hokhikyan; Wenlong Jiang; Ippei Akita; Sina Basir-Kazeruni; Hariprasad Chandrakumar; Dejan Markovic (IEEE Trans. Biomed. Circuits Syst., 2019)

A Feedforward Noise Reduction Technique in Capacitive MEMS Accelerometer Analog Front-End for Ultra-Low-Power IoT Applications. - Ippei Akita; Takayuki Okazawa; Yoshihiko Kurui; Akira Fujimoto; Takashi Asano 002 (IEEE J. Solid State Circuits, 2020)

A 2.6mW 10pTI √ Hz 33kHz Magnetoimpedance-Based Magnetometer with Automatic Loop-Gain and Bandwidth Enhancement. - Ippei Akita; Takeshi Kawano; Hitoshi Aoyama; Shunichi Tatematsu; Masakazu Hioki (ISSCC, 2022)

A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution. - Hiroshi Fuketa; Ippei Akita; Tomohiro Ishikawa; Hanpei Koike; Takahiro Mori (VLSI Technology and Circuits, 2022)

An Automatic Loop Gain Enhancement Technique in Magnetoimpedance-Based Magnetometer. - Ippei Akita; Takeshi Kawano; Hitoshi Aoyama; Shunichi Tatematsu; Masakazu Hioki (IEEE J. Solid State Circuits, 2022)

A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout. - Hiroshi Fuketa; Ippei Akita; Tomohiro Ishikawa; Hanpei Koike; Takahiro Mori (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

3.5 A 4mW 45pT/√Hz Magnetoimpedance-Based ΔΣ Magnetometer with Background Gain Calibration and Short-Time CDS Techniques. - Ippei Akita; Shunichi Tatematsu (ISSCC, 2024)