Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. - Steven Hsu; Amit Agarwal 001; Simeon Realov; Mark A. Anders 001; Gregory K. Chen; Monodeep Kar; Raghavan Kumar; Huseyin Sumbul; Phil C. Knag; Himanshu Kaul; Vikram B. Suresh; Sanu Mathew; et al. (VLSI Circuits, 2020)

Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing. - Wilfred Gomes; Altug Koker; Patrick N. Stover; Doug B. Ingerly; Scott Siers; Srikrishnan Venkataraman; Chris Pelto; Tejas Shah; Amreesh Rao; Frank O'Mahony; Eric Karl; Lance Cheney; et al. (ISSCC, 2022)

Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology. - Yusung Kim 002; Clifford Ong; Anandkumar Mahadevan Pillai; Harish Jagadeesh; Gwanghyeon Baek; Iqbal Rajwani; Zheng Guo; Eric Karl (IEEE J. Solid State Circuits, 2023)