VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers. - Ireneusz Janiszewski; Bernhard Hoppe; Hermann Meuth (DAC, 2001)

Modelling and Simulation in the Design Flow for Numerically Controlled Oscillators. - Ireneusz Janiszewski; Bernhard Hoppe; Hermann Meuth (ESM, 2002)

FPGA-Efficient Hybrid LUT/CORDIC Architecture. - Ireneusz Janiszewski; Hermann Meuth; Bernhard Hoppe (FPL, 2004)

FPGA-efficient phase-to-I/Q architecture. - Ireneusz Janiszewski; Hermann Meuth; Bernhard Hoppe (SoCC, 2004)