Hierarchical Floorplan Design on the Internet. - Jiann-Horng Lin; Jing-Yang Jou; Iris Hui-Ru Jiang (ASP-DAC, 1999)

Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. - Iris Hui-Ru Jiang; Jing-Yang Jou; Yao-Wen Chang (DAC, 1999)

A clustering- and probability-based approach for time-multiplexed FPGA partitioning. - Mango Chia-Tso Chao; Guang-Ming Wu; Iris Hui-Ru Jiang; Yao-Wen Chang (ICCAD, 1999)

Optimum loading dispersion for high-speed tree-type decision circuitry. - Jie-Hong Roland Jiang; Iris Hui-Ru Jiang (ICCAD, 1999)

Optimal reliable crosstalk-driven interconnect optimization. - Iris Hui-Ru Jiang; Song-Ra Pan; Yao-Wen Chang; Jing-Yang Jou (ISPD, 2000)

Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

On placement and routing of wafer scale memory. - Li-An Sung; Iris Hui-Ru Jiang; Yoh-Wen Chang; Jing-Yang Jou; Jiin-Chuan Wu; Tai-Sheng Feng (ICECS, 2001)

Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. - Nicholas Chia-Yuan Chang; Yao-Wen Chang; Iris Hui-Ru Jiang (ISQED, 2002)

Simultaneous floorplanning and buffer block planning. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jing-Yang Jou; Kai-Yuan Chao (ASP-DAC, 2003)

Simultaneous floor plan and buffer-block optimization. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jing-Yang Jou; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design. - Ming-Ching Lu; Meng-Chen Wu; Hung-Ming Chen; Iris Hui-Ru Jiang (SoCC, 2006)

Reliable crosstalk-driven interconnect optimization. - Iris Hui-Ru Jiang; Song-Ra Pan; Yao-Wen Chang; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 2006)

Power-state-aware buffered tree construction. - Iris Hui-Ru Jiang; Ming-Hua Wu (ICCD, 2008)

Configurable rectilinear Steiner tree construction for SoC and nano technologies. - Iris Hui-Ru Jiang; Yen-Ting Yu (ICCD, 2008)

Unification of obstacle-avoiding rectilinear Steiner tree construction. - Iris Hui-Ru Jiang; Shung-Wei Lin; Yen-Ting Yu (SoCC, 2008)

Matching-based minimum-cost spare cell selection for design changes. - Iris Hui-Ru Jiang; Hua-Yu Chang; Liang-Gi Chang; Huang-Bi Hung (DAC, 2009)

VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power. - Wan-Yu Lee; Iris Hui-Ru Jiang (ACM Great Lakes Symposium on VLSI, 2009)

POSA: Power-state-aware Buffered Tree Construction. - Iris Hui-Ru Jiang; Ming-Hua Wu (ISCAS, 2009)

Generic integer linear programming formulation for 3D IC partitioning. - Iris Hui-Ru Jiang (SoCC, 2009)

Live Demo: ECOS 1.0: A metal-only ECO synthesizer. - Iris Hui-Ru Jiang; Hua-Yu Chang (ISCAS, 2010)

Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. - Iris Hui-Ru Jiang; Hua-Yu Chang; Chih-Long Chang (ISPD, 2010)

Analog placement and global routing considering wiring symmetry. - Yu-Ming Yang; Iris Hui-Ru Jiang (ISQED, 2010)

Simultaneous voltage island generation and floorplanning. - Houng-Yi Li; Iris Hui-Ru Jiang; Hung-Ming Chen (SoCC, 2010)

Simultaneous functional and timing ECO. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (DAC, 2011)

INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs. - Iris Hui-Ru Jiang; Chih-Long Chang; Yu-Ming Yang; Evan Y.-W. Tsai; Lancer S.-F. Chen (ISPD, 2011)

3DICE: 3D IC cost evaluation based on fast tier number estimation. - Cheng-Chi Chan; Yen-Ting Yu; Iris Hui-Ru Jiang (ISQED, 2011)

Timing ECO optimization using metal-configurable gate-array spare cells. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (DAC, 2012)

Accurate process-hotspot detection using critical design rule extraction. - Yen-Ting Yu; Ya-Chung Chan; Subarna Sinha; Iris Hui-Ru Jiang; Charles C. Chiang (DAC, 2012)

Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. - Iris Hui-Ru Jiang; Zhuo Li 001; Yih-Lang Li (ICCAD, 2012)

Novel pulsed-latch replacement based on time borrowing and spiral clustering. - Chih-Long Chang; Iris Hui-Ru Jiang; Yu-Ming Yang; Evan Y.-W. Tsai; Aki S.-H. Chen (ISPD, 2012)

Generic Integer Linear Programming Formulation for 3D IC Partitioning. - Wan-Yu Lee; Iris Hui-Ru Jiang; Tsung-Wan Mei (J. Inf. Sci. Eng., 2012)

Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving. - Iris Hui-Ru Jiang; Chih-Long Chang; Yu-Ming Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Reliability-Driven Power/Ground Routing for Analog ICs. - Jing-Wei Lin; Tsung-Yi Ho; Iris Hui-Ru Jiang (ACM Trans. Design Autom. Electr. Syst., 2012)

ECOS: Stable Matching Based Metal-Only ECO Synthesis. - Iris Hui-Ru Jiang; Hua-Yu Chang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

WiT: Optimal Wiring Topology for Electromigration Avoidance. - Iris Hui-Ru Jiang; Hua-Yu Chang; Chih-Long Chang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

The overview of 2013 CAD contest at ICCAD. - Iris Hui-Ru Jiang; Zhuo Li 001; Hwei-Tseng Wang; Natarajan Viswanathan (ICCAD, 2013)

FF-bond: multi-bit flip-flop bonding at placement. - Chang-Cheng Tsai; Yiyu Shi 001; Guojie Luo; Iris Hui-Ru Jiang (ISPD, 2013)

Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating. - Chih-Long Chang; Iris Hui-Ru Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

ECO Optimization Using Metal-Configurable Gate-Array Spare Cells. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Functional ECO Using Metal-Configurable Gate-Array Spare Cells. - Hua-Yu Chang; Iris Hui-Ru Jiang; Yao-Wen Chang (DAC, 2014)

Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations. - Iris Hui-Ru Jiang; Gi-Joon Nam; Hua-Yu Chang; Sani R. Nassif; Jerry Hayes (ICCAD, 2014)

The overview of 2014 CAD contest at ICCAD. - Iris Hui-Ru Jiang; Natarajan Viswanathan; Tai-Chen Chen; Jin-Fu Li 001 (ICCAD, 2014)

iTimerC: common path pessimism removal using effective reduction methods. - Yu-Ming Yang; Yu-Wei Chang; Iris Hui-Ru Jiang (ICCAD, 2014)

DRC-based hotspot detection considering edge tolerance and incomplete specification. - Yen-Ting Yu; Iris Hui-Ru Jiang; Yumin Zhang; Charles C. Chiang (ICCAD, 2014)

PushPull: Short-Path Padding for Timing Error Resilient Circuits. - Yu-Ming Yang; Iris Hui-Ru Jiang; Sung-Ting Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. - An-Che Cheng; Chia-Chih Jack Yen; Celina G. Val; Sam Bayless; Alan J. Hu; Iris Hui-Ru Jiang; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 2014)

Criticality-dependency-aware timing characterization and analysis. - Yu-Ming Yang; King Ho Tam; Iris Hui-Ru Jiang (DAC, 2015)

iTimerC 2.0: Fast Incremental Timing and CPPR Analysis. - Pei-Yu Lee; Iris Hui-Ru Jiang; Cheng-Ruei Li; Wei-Lun Chiu; Yu-Ming Yang (ICCAD, 2015)

GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design. - Chien-Pang Lu; Iris Hui-Ru Jiang; Chin-Hsiung Hsu (ICCAD, 2015)

Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging. - Chang Xu 005; Peixin Li; Guojie Luo; Yiyu Shi 001; Iris Hui-Ru Jiang (ISPD, 2015)

Feature detection for image analytics via FPGA acceleration. - Hua-Yu Chang; Iris Hui-Ru Jiang; H. Peter Hofstee; Damir A. Jamsek; Gi-Joon Nam (IBM J. Res. Dev., 2015)

Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction. - Yen-Ting Yu; Geng-He Lin; Iris Hui-Ru Jiang; Charles C. Chiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. - Ulf Schlichtmann; Masanori Hashimoto; Iris Hui-Ru Jiang; Bing Li 005 (ASP-DAC, 2016)

Multiple patterning layout decomposition considering complex coloring rules. - Hua-Yu Chang; Iris Hui-Ru Jiang (DAC, 2016)

Resource-aware functional ECO patch generation. - An-Che Cheng; Iris Hui-Ru Jiang; Jing-Yang Jou (DATE, 2016)

OpenDesign flow database: the infrastructure for VLSI design and design automation research. - Jinwook Jung; Iris Hui-Ru Jiang; Gi-Joon Nam; Victor N. Kravets; Laleh Behjat; Yih-Lang Li (ICCAD, 2016)

OWARU: free space-aware timing-driven incremental placement. - Jinwook Jung; Gi-Joon Nam; Lakshmi N. Reddy; Iris Hui-Ru Jiang; Youngsoo Shin (ICCAD, 2016)

Analytical Clustering Score with Application to Postplacement Register Clustering. - Chang Xu 005; Guojie Luo; Peixin Li; Yiyu Shi 001; Iris Hui-Ru Jiang (ACM Trans. Design Autom. Electr. Syst., 2016)

iClaire: A Fast and General Layout Pattern Classification Algorithm. - Wei-Chun Chang; Iris Hui-Ru Jiang; Yen-Ting Yu; Wei-Fang Liu (DAC, 2017)

Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation. - Wei-Lun Chiu; Iris Hui-Ru Jiang; Chien-Pang Lu; Yu-Tung Chang (DAC, 2017)

Fast low power rule checking for multiple power domain design. - Chien-Pang Lu; Iris Hui-Ru Jiang (DATE, 2017)

DATC RDF: Robust design flow database: Invited paper. - Jinwook Jung; Pei-Yu Lee; Yan-Shiun Wu; Nima Karimpour Darav; Iris Hui-Ru Jiang; Victor N. Kravets; Laleh Behjat; Yih-Lang Li; Gi-Joon Nam (ICCAD, 2017)

iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis. - Pei-Yu Lee; Iris Hui-Ru Jiang; Ting-You Yang (ISPD, 2017)

Multiple Patterning Layout Decomposition Considering Complex Coloring Rules and Density Balancing. - Iris Hui-Ru Jiang; Hua-Yu Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

FastPass: Fast timing path search for generalized timing exception handling. - Pei-Yu Lee; Iris Hui-Ru Jiang; Tung-Chieh Chen (ASP-DAC, 2018)

COSAT: congestion, obstacle, and slew aware tree construction for multiple power domain design. - Chien-Pang Lu; Iris Hui-Ru Jiang (DAC, 2018)

DATC RDF: an academic flow from logic synthesis to detailed routing. - Jinwook Jung; Iris Hui-Ru Jiang; Jianli Chen; Shih-Ting Lin; Yih-Lang Li; Victor N. Kravets; Gi-Joon Nam (ICCAD, 2018)

Recent Research and Challenges in Multiple Patterning Layout Decomposition. - Iris Hui-Ru Jiang; Hua-Yu Chang (ISVLSI, 2018)

Timing Macro Modeling for Efficient Hierarchical Timing Analysis. - Iris Hui-Ru Jiang; Pei-Yu Lee (ISVLSI, 2018)

OpenMPL: An Open Source Layout Decomposer. - Qi Sun 002; Yibo Lin; Iris Hui-Ru Jiang; Bei Yu 001; David Z. Pan (CoRR, 2018)

DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing. - Jinwook Jung; Iris Hui-Ru Jiang; Jianli Chen; Shih-Ting Lin; Yih-Lang Li; Victor N. Kravets; Gi-Joon Nam (CoRR, 2018)

OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing. - Jinwook Jung; Gi-Joon Nam; Lakshmi N. Reddy; Iris Hui-Ru Jiang; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis. - Pei-Yu Lee; Iris Hui-Ru Jiang (ACM Trans. Design Autom. Electr. Syst., 2018)

OpenMPL: An Open Source Layout Decomposer: Invited Paper. - Wei Li 159; Yuzhe Ma; Qi Sun 002; Yibo Lin; Iris Hui-Ru Jiang; Bei Yu 001; David Z. Pan (ASICON, 2019)

DATC RDF-2019: Towards a Complete Academic Reference Design Flow. - Jianli Chen; Iris Hui-Ru Jiang; Jinwook Jung; Andrew B. Kahng; Victor N. Kravets; Yih-Lang Li; Shih-Ting Lin; Mingyu Woo (ICCAD, 2019)

Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement. - Hua-Yu Chang; Iris Hui-Ru Jiang (ISPD, 2019)

Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing. - Ya-Chu Chang; Tung-Wei Lin; Iris Hui-Ru Jiang; Gi-Joon Nam (ISPD, 2019)

Graph-Based Modeling, Scheduling, and Verification for Intersection Management of Intelligent Vehicles. - Yi-Ting Lin; Hsiang Hsu; Shang-Chien Lin; Chung-Wei Lin; Iris Hui-Ru Jiang; Changliu Liu (ACM Trans. Embed. Comput. Syst., 2019)

Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability. - Sheng-Jung Yu; Chen-Chien Kao; Chia-Han Huang; Iris Hui-Ru Jiang (ASP-DAC, 2020)

Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net Structures. - Hsien-Han Cheng; Iris Hui-Ru Jiang; Oscar Ou (DAC, 2020)

Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA Systems. - Tung-Wei Lin; Wei-Chen Tai; Yu-Cheng Lin; Iris Hui-Ru Jiang (DAC, 2020)

Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization. - Chien-Pang Lu; Iris Hui-Ru Jiang; Chih-Wen Yang (DAC, 2020)

DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. - Jianli Chen; Iris Hui-Ru Jiang; Jinwook Jung; Andrew B. Kahng; Victor N. Kravets; Yih-Lang Li; Shih-Ting Lin; Mingyu Woo (ICCAD, 2020)

Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance. - Xuan-Xue Huang; Hsien-Chia Chen; Sheng-Wei Wang; Iris Hui-Ru Jiang; Yih-Chih Chou; Cheng-Hong Tsai (ICCAD, 2020)

Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Chung-Ping Chen (ICCAD, 2020)

A Dynamic Programming Approach to Optimal Lane Merging of Connected and Autonomous Vehicles. - Shang-Chien Lin; Hsiang Hsu; Yi-Ting Lin; Chung-Wei Lin; Iris Hui-Ru Jiang; Changliu Liu (IV, 2020)

iClaire: A Fast and General Layout Pattern Classification Algorithm With Clip Shifting and Centroid Recreation. - Wei-Chun Chang; Iris Hui-Ru Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval. - Sean Shang-En Tseng; Iris Hui-Ru Jiang; James P. Shiely (DAC, 2021)

DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. - Jianli Chen; Iris Hui-Ru Jiang; Jinwook Jung; Andrew B. Kahng; Seungwon Kim; Victor N. Kravets; Yih-Lang Li; Ravi Varadarajan; Mingyu Woo (ICCAD, 2021)

Opportunities for 2.5/3D Heterogeneous SoC Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Chung-Ping Chen (VLSI-DAT, 2021)

Efficient Mandatory Lane Changing of Connected and Autonomous Vehicles. - Shang-Chien Lin; Chia-Chu Kung; Lee Lin; Chung-Wei Lin; Iris Hui-Ru Jiang (VTC Fall, 2021)

OpenMPL: An Open-Source Layout Decomposer. - Wei Li 159; Yuzhe Ma; Qi Sun 002; Lu Zhang; Yibo Lin; Iris Hui-Ru Jiang; Bei Yu 001; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials. - Yi-Ting Lin; Iris Hui-Ru Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Timing macro modeling with graph neural networks. - Kevin Kai-Chun Chang; Chun-Yao Chiang; Pei-Yu Lee; Iris Hui-Ru Jiang (DAC, 2022)

Many-Layer Hotspot Detection by Layer-Attentioned Visual Question Answering. - Yen-Shuo Chen; Iris Hui-Ru Jiang (DATE, 2022)

Deadlock Analysis and Prevention for Intersection Management Based on Colored Timed Petri Nets. - Tsung-Lin Tsou; Chung-Wei Lin; Iris Hui-Ru Jiang (DATE, 2022)

Sub-Resolution Assist Feature Generation with Reinforcement Learning and Transfer Learning. - Guan-Ting Liu; Wei-Chen Tai; Yi-Ting Lin; Iris Hui-Ru Jiang; James P. Shiely; Pu-Jen Cheng (ICCAD, 2022)

Intelligent Design Automation for Heterogeneous Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Charlie Chung-Ping Chen (ISPD, 2022)

Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines. - Chien-Pang Lu; Iris Hui-Ru Jiang; Chih-Wen Yang (ISPD, 2022)

Deadlock Resolution for Intelligent Intersection Management with Changeable Trajectories. - Li-Heng Lin; Kuan-Chun Wang; Ying-Hua Lee; Kai-En Lin; Chung-Wei Lin; Iris Hui-Ru Jiang (IV, 2022)

Lightning Talk: All Routes to Timing Closure. - Iris Hui-Ru Jiang (DAC, 2023)

EDA for Domain Specific Computing: An Introduction for the Panel. - Iris Hui-Ru Jiang; David G. Chinnery (ISPD, 2023)

Introduction to the Special Section on Advances in Physical Design Automation. - Iris Hui-Ru Jiang; David G. Chinnery; Gracieli Posser; Jens Lienig (ACM Trans. Design Autom. Electr. Syst., 2023)

Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree Techniques. - Chen-Ho Chen; Chien-Nan Jimmy Liu; Wei-Ting Tu; Tung-Chieh Chen; Iris Hui-Ru Jiang (APCCAS, 2024)

Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules. - Yu-Yang Chen; Yi-Chen Lin; Tzu-Han Hsu; Iris Hui-Ru Jiang; Tung-Chieh Chen; Tai-Chen Chen; Hua-Yu Chang (ICCAD, 2024)

Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-Flops. - Yen-Yu Chen; Hao-Yu Wu; Iris Hui-Ru Jiang; Cheng-Hong Tsai; Chien-Cheng Wu (ISPD, 2024)

Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization. - Chien-Pang Lu; Iris Hui-Ru Jiang; Chung-Ching Peng; Mohd Mawardi Mohd Razha; Alessandro Uber (ISPD, 2024)

Novel Airgap Insertion and Layer Reassignment for Timing Optimization Guided by Slack Dependency. - Wei-Chen Tai; Min-Hsien Chung; Iris Hui-Ru Jiang (ISPD, 2024)

Graph-Based Deadlock Analysis and Prevention for Robust Intelligent Intersection Management. - Kai-En Lin; Kuan-Chun Wang; Yu-Heng Chen; Li-Heng Lin; Ying-Hua Lee; Chung-Wei Lin; Iris Hui-Ru Jiang (ACM Trans. Cyber Phys. Syst., 2024)

Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective. - Kevin Kai-Chun Chang; Guan-Ting Liu; Chun-Yao Chiang; Pei-Yu Lee; Iris Hui-Ru Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Multi-Stage CSM Timing Waveform Propagation Accelerated by NLDM Assistance. - Shih-Kai Lee; Pei-Yu Lee; Iris Hui-Ru Jiang (ISPD, 2025)

Graceful Register Clustering and Rebanking for Power and Timing Balancing. - Yi-Ting Hsieh; Tung-Wei Lin; Ya-Chu Chang; Hao-Yu Wu; Iris Hui-Ru Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process. - Yi-Ting Lin; Kang-Ting Fan; Iris Hui-Ru Jiang (ACM Trans. Design Autom. Electr. Syst., 2025)