On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1991)

Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1991)

Test Generation for Synchronous Sequential Circuits Based on Fault Extraction. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1991)

Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. - Irith Pomeranz; Sudhakar M. Reddy; Lakshmi N. Reddy (ICCAD, 1991)

Testing of Fault-Tolerant Hardware. - Irith Pomeranz; Sudhakar M. Reddy (Fault-Tolerant Computing Systems, 1991)

Achieving Complete Delay Fault Testability by Extra Inputs. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1991)

COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. - Irith Pomeranz; Lakshmi N. Reddy; Sudhakar M. Reddy (ITC, 1991)

The minimum test set problem for circuits with nonreconvergent fanout. - Irith Pomeranz; Zvi Kohavi (J. Electron. Test., 1991)

Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion. - Irith Pomeranz; Zvi Kohavi (IEEE Trans. Computers, 1991)

State Assignment Using Input/Output Functions. - Irith Pomeranz; Kwang-Ting Cheng (DAC, 1992)

At-Speed Delay Testing of Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1992)

SPADES: a simulator for path delay faults in sequential circuits. - Irith Pomeranz; Lakshmi N. Reddy; Sudhakar M. Reddy (EURO-DAC, 1992)

Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. - Niraj K. Jha; Irith Pomeranz; Sudhakar M. Reddy; Robert J. Miller (FTCS, 1992)

A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1992)

On the generation of small dictionaries for fault location. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1992)

An efficient non-enumerative method to estimate path delay fault coverage. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1992)

COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. - Lakshmi N. Reddy; Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1992)

Effect of Communication in a Parallel Genetic Algorithm. - Venkataramana Kommu; Irith Pomeranz (ICPP (3), 1992)

3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1992)

Generalization of independent faults for transition faults. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1992)

The Multiple Observation Time Test Strategy. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1992)

A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion. - Irith Pomeranz; Zvi Kohavi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1993)

NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. - Irith Pomeranz; Sudhakar M. Reddy; Prasanti Uppaluri (DAC, 1993)

GAFPGA: Genetic algorithm for FPGA technology mapping. - Venkataramana Kommu; Irith Pomeranz (EURO-DAC, 1993)

A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis. - Irith Pomeranz; Sudhakar M. Reddy (EURO-DAC, 1993)

EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1993)

Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1993)

Theory and Practice of Sequential Machine Testing and Testability. - Irith Pomeranz; Sudhakar M. Reddy; Janak H. Patel (FTCS, 1993)

Test generation for path delay faults based on learning. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1993)

On diagnosis and correction of design errors. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1993)

Fault dictionary compression and equivalence class computation for sequential circuits. - Paul G. Ryan; W. Kent Fuchs; Irith Pomeranz (ICCAD, 1993)

A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1993)

On the Generation of Weights for Weighted Pseudo Random Testing. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1993)

Classification of Faults in Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1993)

Testing of Fault-Tolerant Hardware Through Partial Control of Inputs. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1993)

STOIC: state assignment based on output/input functions. - Irith Pomeranz; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

COMPACTEST: a method to generate compact test sets for combinational circuits. - Irith Pomeranz; Lakshmi N. Reddy; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1994)

On Improving Fault Diagnosis for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1994)

On Codeword Testing of Two-Rail and Parity TSC Checkers. - Sudhakar M. Reddy; Irith Pomeranz; Rahul Jain 014 (FTCS, 1994)

Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times. - Prasanti Uppaluri; Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1994)

On testing delay faults in macro-based combinational circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1994)

On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1994)

On compacting test sets by addition and removal of test vectors. - Seiji Kajihara; Irith Pomeranz; Kozo Kinoshita; Sudhakar M. Reddy (VTS, 1994)

On identifying undetectable and redundant faults in synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1994)

Application of Homing Sequences to Synchronous Sequential Circuit Testing. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1994)

On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1994)

An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

On achieving complete fault coverage for sequential machines. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

On determining symmetries in inputs of logic circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Static compaction for two-pattern test sets. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1995)

On Synthesis-for-Testability of Combinational Logic Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1995)

On generating compact test sequences for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (EURO-DAC, 1995)

Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1995)

MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. - Sitaran Yadavalli; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1995)

Compact test generation for bridging faults under IDDQ testing. - Remata S. Reddy; Irith Pomeranz; Sudhakar M. Reddy; Seiji Kajihara (VTS, 1995)

An optimal algorithm for cycle breaking in directed graphs. - Tatiana Orenstein; Zvi Kohavi; Irith Pomeranz (J. Electron. Test., 1995)

Aliasing Computation Using Fault Simulation with Fault Dropping. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1995)

On Fault Simulation for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1995)

INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1995)

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. - Seiji Kajihara; Irith Pomeranz; Kozo Kinoshita; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

On correction of multiple design errors. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

NEST: a nonenumerative test generation method for path delay faults in combinational circuits. - Irith Pomeranz; Sudhakar M. Reddy; Prasanti Uppaluri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1996)

Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1996)

On Static Compaction of Test Sequences for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1996)

On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem. - Irith Pomeranz; Sudhakar M. Reddy (ED&TC, 1996)

Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1996)

On Double Transition Faults as a Delay Fault Model. - Irith Pomeranz; Sudhakar M. Reddy; Janak H. Patel (Great Lakes Symposium on VLSI, 1996)

Fault Location Based on Circuit Partitioning. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 1996)

On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1996)

Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor. - Irith Pomeranz; Nirmal R. Saxena; Richard Reeve; Paritosh Kulkarni; Yan A. Li (ITC, 1996)

On Potential Fault Detection in Sequential Circuits. - Elizabeth M. Rudnick; Janak H. Patel; Irith Pomeranz (ITC, 1996)

On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1996)

Synchronization of large sequential circuits by partial reset. - Yuan Lu; Irith Pomeranz (VTS, 1996)

On the effects of test compaction on defect coverage. - Sudhakar M. Reddy; Irith Pomeranz; Seiji Kajihara (VTS, 1996)

On minimizing the number of test points needed to achieve complete robust path delay fault testability. - Prasanti Uppaluri; Uwe Sparmann; Irith Pomeranz (VTS, 1996)

On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1996)

On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1996)

On the Compaction of Test Sets Produced by Genetic Optimization. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1997)

TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1997)

Fault Simulation under the Multiple Observation Time Approach using Backward Implications. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1997)

On improving genetic optimization based test generation. - Irith Pomeranz; Sudhakar M. Reddy (ED&TC, 1997)

On the use of reset to increase the testability of interconnected finite-state machines. - Irith Pomeranz; Sudhakar M. Reddy (ED&TC, 1997)

ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1997)

On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. - Irith Pomeranz; Sudhakar M. Reddy (Great Lakes Symposium on VLSI, 1997)

Built-in test generation for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1997)

Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 1997)

A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. - Seiji Kajihara; Kozo Kinoshita; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1997)

On the Detection of Reset Faults in Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1997)

On Full Reset as a Design-For-Testability Technique. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1997)

EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1997)

On n-detection test sequences for synchronous sequential circuits343. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1997)

On Dictionary-Based Fault Location in Digital Logic Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1997)

Test Generation for Multiple State-Table Faults in Finite-State Machines. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1997)

LOCSTEP: a logic-simulation-based test generation procedure. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

On error correction in macro-based circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Compact test sets for high defect coverage. - Sudhakar M. Reddy; Irith Pomeranz; Seiji Kajihara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . - Ruifeng Guo; Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1998)

A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination. - Irith Pomeranz; W. Kent Fuchs (Asian Test Symposium, 1998)

Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1998)

Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. - Ruifeng Guo; Irith Pomeranz; Sudhakar M. Reddy (DATE, 1998)

A Synthesis Procedure for Flexible Logic Functions. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 1998)

Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 1998)

A Generalized Test Generation Procedure for Path Delay Faults. - Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1998)

Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. - Irith Pomeranz; Sudhakar M. Reddy (Great Lakes Symposium on VLSI, 1998)

On finding undetectable and redundant faults in synchronous sequential circuits. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (ICCD, 1998)

Improved built-in test pattern generators based on comparison units for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 1998)

A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1998)

MIX: A Test Generation System for Synchronous Sequential Circuits. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1998)

On Test Compaction Objectives for Combinational and Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1998)

On Removing Redundant Faults in Synchronous Sequential Circuits. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (VTS, 1998)

On Synchronizing Sequences and Test Sequence Partitioning. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1998)

Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1998)

Delay fault models for VLSI circuits1. - Irith Pomeranz; Sudhakar M. Reddy (Integr., 1998)

Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1998)

Techniques for minimizing power dissipation in scan and combinational circuits during test application. - Vinay Dabholkar; Sreejit Chakravarty; Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Design-for-testability for path delay faults in large combinational circuits using test points. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Test sequences to achieve high defect coverage for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Functional test generation for delay faults in combinational circuits. - Irith Pomeranz; Sudhakar M. Reddy (ACM Trans. Design Autom. Electr. Syst., 1998)

On methods to match a test pattern generator to a circuit-under-test. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Vector-Based Functional Fault Models for Delay Faults. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1999)

Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 1999)

Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. - Ruifeng Guo; Sudhakar M. Reddy; Irith Pomeranz (DAC, 1999)

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 1999)

Full Scan Fault Coverage With Partial Scan. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (DATE, 1999)

On avoiding undetectable faults during test generation. - Irith Pomeranz; Sudhakar M. Reddy (ETW, 1999)

PASTA: Partial Scan to Enhance Test Compaction. - Irith Pomeranz; Sudhakar M. Reddy (Great Lakes Symposium on VLSI, 1999)

Techniques for improving the efficiency of sequential circuit test generation. - Xijiang Lin; Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1999)

An approach for improving the levels of compaction achieved by vector omission. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 1999)

Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 1999)

On achieving complete coverage of delay faults in full scan circuits using locally available lines. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 1999)

The effects of test compaction on fault diagnosis. - Yun Shao 002; Ruifeng Guo; Sudhakar M. Reddy; Irith Pomeranz (ITC, 1999)

VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1999)

Implication and Evaluation Techniques for Proving Fault Equivalence. - M. Enamul Amyeen; W. Kent Fuchs; Irith Pomeranz; Vamsi Boppana (VTS, 1999)

A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. - Ruifeng Guo; Irith Pomeranz; Sudhakar M. Reddy (VTS, 1999)

A Flexible Path Selection Procedure for Path Delay Fault Testing. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1999)

On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 1999)

Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. - Irith Pomeranz; Yervant Zorian (VTS, 1999)

Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. - Sudhakar M. Reddy; Irith Pomeranz; Nadir Z. Basturkmen; Xijiang Lin (VTS, 1999)

A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 1999)

A comment on "Improving a nonenumerative method to estimate path delay fault coverage". - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Static test compaction for synchronous sequential circuits based on vector restoration. - Irith Pomeranz; Sudhakar M. Reddy; Ruifeng Guo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Enhanced untestable path analysis using edge graphs. - Seiji Kajihara; Takashi Shimono; Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2000)

On the feasibility of fault simulation using partial circuit descriptions. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2000)

Reducing test application time for full scan circuits by the addition of transfer sequences. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2000)

On diagnosis of pattern-dependent delay faults. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 2000)

Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2000)

Functional Test Generation for Full Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2000)

Test-Point Insertion to Enhance Test Compaction for Scan Designs. - Irith Pomeranz; Sudhakar M. Reddy (DSN, 2000)

On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (ETW, 2000)

Improving the Proportion of At-Speed Tests in Scan BIST. - Yu Huang 005; Irith Pomeranz; Sudhakar M. Reddy; Janusz Rajski (ICCAD, 2000)

Simulation Based Test Generation for Scan Designs. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 2000)

Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2000)

On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2000)

Selection of potentially testable path delay faults for test generation. - Atsushi Murakami; Seiji Kajihara; Tsutomu Sasao; Irith Pomeranz; Sudhakar M. Reddy (ITC, 2000)

On validating data hold times for flip-flops in sequential circuits. - Sudhakar M. Reddy; Irith Pomeranz; Seiji Kajihara; Atsushi Murakami; Sadami Takeoka; Mitsuyasu Ohta (ITC, 2000)

Fault diagnosis based on parameters of output responses. - Irith Pomeranz; Sudhakar M. Reddy (PRDC, 2000)

Test Transformation to Improve Compaction by Statistical Encoding. - Hideyuki Ichihara; Kozo Kinoshita; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2000)

On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2000)

SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. - Xijiang Lin; Wu-Tung Cheng; Irith Pomeranz; Sudhakar M. Reddy (VTS, 2000)

Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. - Irith Pomeranz; Sudhakar M. Reddy (J. Electron. Test., 2000)

On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2000)

On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2000)

Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2000)

On n-detection test sets and variable n-detection test sets fortransition faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

On synchronizable circuits and their synchronizing sequences. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. - Ruifeng Guo; Sudhakar M. Reddy; Irith Pomeranz (Asian Test Symposium, 2001)

On Pass/Fail Dictionaries for Scan Circuits . - Irith Pomeranz (Asian Test Symposium, 2001)

A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2001)

Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. - Irith Pomeranz; Sudhakar M. Reddy; Xijiang Lin (Asian Test Symposium, 2001)

An Efficient Method to Identify Untestable Path Delay Faults. - Yun Shao 002; Sudhakar M. Reddy; Seiji Kajihara; Irith Pomeranz (Asian Test Symposium, 2001)

Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits. - Irith Pomeranz (DAC, 2001)

An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 2001)

Sequence reordering to improve the levels of compaction achievable by static compaction procedures. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2001)

Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2001)

ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (ACM Great Lakes Symposium on VLSI, 2001)

Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description. - Irith Pomeranz; Sudhakar M. Reddy (HLDVT, 2001)

REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits. - Chen Wang 014; Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 2001)

COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2001)

A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2001)

On static test compaction and test pattern ordering for scan designs. - Xijiang Lin; Janusz Rajski; Irith Pomeranz; Sudhakar M. Reddy (ITC, 2001)

A method to enhance the fault coverage obtained by output response comparison of identical circuits. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 2001)

On Improving Static Test Compaction for Sequential Circuits. - Ruifeng Guo; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2001)

Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. - M. Enamul Amyeen; W. Kent Fuchs; Irith Pomeranz; Vamsi Boppana (VTS, 2001)

On the Use of Fault Dominance in n-Detection Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2001)

Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits. - Irith Pomeranz; Sudhakar M. Reddy (J. Syst. Archit., 2001)

Vector replacement to improve static-test compaction forsynchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

On diagnosis and diagnostic test generation for pattern-dependenttransition faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Forward-looking fault simulation for improved static compaction. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Testing of scan circuits containing nonisolated random-logic legacycores. - Irith Pomeranz; Y. Zonan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

A built-in self-test method for diagnosis of synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Test Data Compression Using Don?t-Care Identification and Statistical Encoding. - Seiji Kajihara; Kenjiro Taniguchi; Kohei Miyase; Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2002)

Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. - Ilia Polian; Irith Pomeranz; Bernd Becker 001 (Asian Test Symposium, 2002)

Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2002)

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2002)

On Generating High Quality Tests for Transition Faults. - Yun Shao 002; Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2002)

On output response compression in the presence of unknown output values. - Irith Pomeranz; Sandip Kundu; Sudhakar M. Reddy (DAC, 2002)

Finding a Common Fault Response for Diagnosis during Silicon Debug. - Irith Pomeranz; Janusz Rajski; Sudhakar M. Reddy (DATE, 2002)

Fault Isolation Using Tests for Non-Isolated Blocks. - Irith Pomeranz; Yervant Zorian (DATE, 2002)

Test Data Compression Using Don't-Care Identification and Statistical Encoding. - Seiji Kajihara; Kenjiro Taniguchi; Irith Pomeranz; Sudhakar M. Reddy (DELTA, 2002)

Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DELTA, 2002)

On undetectable faults in partial scan circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 2002)

Conflict driven techniques for improving deterministic test pattern generation. - Chen Wang 014; Sudhakar M. Reddy; Irith Pomeranz; Xijiang Lin; Janusz Rajski (ICCAD, 2002)

Don't-Care Identification on Specific Bits of Test Patterns. - Kohei Miyase; Seiji Kajihara; Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2002)

On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2002)

Transient-Fault Recovery Using Simultaneous Multithreading. - T. N. Vijaykumar; Irith Pomeranz; Karl Cheng (ISCA, 2002)

Pseudo Random Patterns Using Markov Sources for Scan BIST. - Nadir Z. Basturkmen; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2002)

On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. - Sudhakar M. Reddy; Irith Pomeranz; Huaxing Tang; Seiji Kajihara; Kozo Kinoshita (ITC, 2002)

A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC/VLSI Design, 2002)

Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. - Yun Shao 002; Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC/VLSI Design, 2002)

Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits. - M. Enamul Amyeen; Irith Pomeranz; W. Kent Fuchs (VTS, 2002)

Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2002)

Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2002)

A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2002)

On the use of random limited-scan to improve at-speed randompattern testing of scan circuits. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

n-pass n-detection fault simulation and its applications. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

A DFT Approach for Path Delay Faults in Interconnected Circuits. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2003)

Test Data Volume Reduction by Test Data Realignment. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2003)

A scan BIST generation method using a markov source and partial bit-fixing. - Wei Li 023; Chaowen Yu; Sudhakar M. Reddy; Irith Pomeranz (DAC, 2003)

On test data compression and n-detection test sets. - Irith Pomeranz; Sudhakar M. Reddy (DAC, 2003)

A New Approach to Test Generation and Test Compaction for Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2003)

Test Data Compression Based on Output Dependence. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2003)

On the Characterization of Hard-to-Detect Bridging Faults. - Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (DATE, 2003)

On path selection for delay fault testing considering operating conditions [logic IC testing]. - Bharath Seshadri; Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (ETW, 2003)

On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 2003)

On Compacting Test Response Data Containing Unknown Values. - Chen Wang 014; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski; Jerzy Tyszer (ICCAD, 2003)

Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz (ICCD, 2003)

A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. - Yoshinobu Higami; Shin-ya Kobayashi; Yuzo Takamatsu; Seiji Kajihara; Irith Pomeranz (ICCD, 2003)

Static Test Compaction for Multiple Full-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2003)

An Improved Markov Source Design for Scan BIST. - Chaowen Yu; Wei Li 023; Sudhakar M. Reddy; Irith Pomeranz (IOLTS, 2003)

On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. - Masao Naruse; Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (ITC, 2003)

Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains. - Irith Pomeranz (ITC, 2003)

On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. - Huaxing Tang; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2003)

Optimizing SOC Test Resources Using Dual Sequences. - Wei Zou; Chris C. N. Chu; Sudhakar M. Reddy; Irith Pomeranz (VLSI-SoC (Selected Papers), 2003)

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2003)

GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. - Ganesh Venkataraman; Sudhakar M. Reddy; Irith Pomeranz (VLSI Design, 2003)

A Test Interface for Built-In Test of Non-Isolated Scanned Cores. - Irith Pomeranz; Sudhakar M. Reddy; Yervant Zorian (VTS, 2003)

Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. - Xiaoming Yu; M. Enamul Amyeen; Srikanth Venkataraman; Ruifeng Guo; Irith Pomeranz (VTS, 2003)

SOC Test Scheduling Using Simulated Annealing. - Wei Zou; Sudhakar M. Reddy; Irith Pomeranz; Yu Huang 005 (VTS, 2003)

A Low Power Pseudo-Random BIST Technique. - Nadir Z. Basturkmen; Sudhakar M. Reddy; Irith Pomeranz (J. Electron. Test., 2003)

On Selecting Testable Paths in Scan Designs. - Yun Shao 002; Sudhakar M. Reddy; Irith Pomeranz; Seiji Kajihara (J. Electron. Test., 2003)

Transient-Fault Recovery for Chip Multiprocessors. - Mohamed A. Gomaa; Chad Scarbrough; T. N. Vijaykumar; Irith Pomeranz (IEEE Micro, 2003)

Fault equivalence identification in combinational circuits using implication and evaluation techniques. - M. Enamul Amyeen; W. Kent Fuchs; Irith Pomeranz; Vamsi Boppana (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Reverse-order-restoration-based static test compaction for synchronous sequential circuits. - Ruifeng Guo; Sudhakar M. Reddy; Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

PROPTEST: a property-based test generator for synchronous sequential circuits. - Ruifeng Guo; Sudhakar M. Reddy; Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Test enrichment for path delay faults using multiple sets of target faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Theorems for identifying undetectable faults in partial-scan circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Test data compression based on input-output dependence. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

On test data volume reduction for multiple scan chain designs. - Sudhakar M. Reddy; Kohei Miyase; Seiji Kajihara; Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2003)

Properties of Maximally Dominating Faults. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2004)

A Postprocessing Procedure of Test Enrichment for Path Delay Faults. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2004)

Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. - Chaowen Yu; Sudhakar M. Reddy; Irith Pomeranz (Asian Test Symposium, 2004)

On test generation for transition faults with minimized peak power dissipation. - Wei Li 023; Sudhakar M. Reddy; Irith Pomeranz (DAC, 2004)

On the generation of scan-based test sets with reachable states for testing under functional operation conditions. - Irith Pomeranz (DAC, 2004)

Scan-BIST based on transition probabilities. - Irith Pomeranz (DAC, 2004)

Level of Similarity: A Metric for Fault Collapsing. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2004)

Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. - Irith Pomeranz; Srikanth Venkataraman; Sudhakar M. Reddy; Bharath Seshadri (DATE, 2004)

Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2004)

Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2004)

On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan. - Irith Pomeranz; Sudhakar M. Reddy (ICCD, 2004)

Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. - Yonsang Cho; Irith Pomeranz; Sudhakar M. Reddy (ISQED, 2004)

Scan BIST Targeting Transition Faults Using a Markov Source. - Hangkyu Lee; Irith Pomeranz; Sudhakar M. Reddy (ISQED, 2004)

Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. - Irith Pomeranz; Srikanth Venkataraman; Sudhakar M. Reddy (ITC, 2004)

On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2004)

Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. - Irith Pomeranz; Srikanth Venkataraman; Sudhakar M. Reddy; M. Enamul Amyeen (VLSI Design, 2004)

Don't Care Identification and Statistical Encoding for Test Data Compression. - Seiji Kajihara; Kenjiro Taniguchi; Kohei Miyase; Irith Pomeranz; Sudhakar M. Reddy (IEICE Trans. Inf. Syst., 2004)

Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. - Irith Pomeranz; Sandip Kundu; Sudhakar M. Reddy (IEEE Trans. Computers, 2004)

On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2004)

A Measure of Quality for n-Detection Test Sets. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2004)

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2004)

Constrained test generation for embedded synchronous sequential circuits with serial-input access. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Vector-restoration-based static compaction using random initial omission. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

On the characterization and efficient computation of hard-to-detect bridging faults. - Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Fault isolation for nonisolated blocks. - Irith Pomeranz; Yervant Zorian (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. - Narendra Devta-Prasanna; Sudhakar M. Reddy; Arun Gunda; P. Krishnamurthy; Irith Pomeranz (Asian Test Symposium, 2005)

Circuit Independent Weighted Pseudo-Random BIST Pattern Generator. - Chaowen Yu; Sudhakar M. Reddy; Irith Pomeranz (Asian Test Symposium, 2005)

N-detection under transparent-scan. - Irith Pomeranz (DAC, 2005)

Worst-Case and Average-Case Analysis of n-Detection Test Sets. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2005)

The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2005)

Defect Aware Test Patterns. - Huaxing Tang; Gang Chen 011; Sudhakar M. Reddy; Chen Wang 014; Janusz Rajski; Irith Pomeranz (DATE, 2005)

Recovery During Concurrent On-Line Testing of Identical Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2005)

On Generating Pseudo-Functional Delay Fault Tests for Scan Designs. - Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2005)

A unified fault model and test generation procedure for interconnect opens and bridges. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski; Piet Engelke; Bernd Becker 001 (ETS, 2005)

Using dummy bridging faults to define a reduced set of target faults. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2005)

Path-oriented transition fault test generation considering operating conditions. - Bharath Seshadri; Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (ETS, 2005)

A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (ICCD, 2005)

Battery-aware dynamic voltage scaling in multiprocessor embedded system. - Yuan Cai; Sudhakar M. Reddy; Irith Pomeranz; Bashir M. Al-Hashimi (ISCAS (1), 2005)

Dynamic Test Compaction for Bridging Faults. - Irith Pomeranz; Sudhakar M. Reddy (ISQED, 2005)

On Reducing Peak Current and Power during Test. - Wei Li 023; Sudhakar M. Reddy; Irith Pomeranz (ISVLSI, 2005)

Fault Diagnosis and Fault Model Aliasing. - Irith Pomeranz; Srikanth Venkataraman; Sudhakar M. Reddy (ISVLSI, 2005)

Methods for improving transition delay fault coverage using broadside tests. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2005)

Forming N-detection test sets from one-detection test sets without test generation. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 2005)

Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2005)

On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. - Huaxing Tang; Chen Wang 014; Janusz Rajski; Sudhakar M. Reddy; Jerzy Tyszer; Irith Pomeranz (VLSI Design, 2005)

On reducing test application time for scan circuits using limited scan operations and transfer sequences. - Yonsang Cho; Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

On fault equivalence, fault dominance, and incompletely specified test sets. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Dependable Secur. Comput., 2005)

Autoscan: a scan design without external scan inputs or outputs. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2005)

To Overtest Or Not To Overtest - More Questions Than Answers. - Irith Pomeranz (ATS, 2006)

A Functional Fault Model with Implicit Fault Effect Propagation Requirements. - Irith Pomeranz; Srinivas Patil; Praveen Parvathala (ATS, 2006)

On the Replacement of Scan Chain Inputs by Primary Input Vectors. - Irith Pomeranz; Sudhakar M. Reddy (ATS, 2006)

A test pattern ordering algorithm for diagnosis with truncated fail data. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (DAC, 2006)

Test compaction for transition faults under transparent-scan. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2006)

Test Generation for Open Defects in CMOS Circuits. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2006)

Selecting High-Quality Delay Tests for Manufacturing Test and Debug. - Hangkyu Lee; Suriyaprakash Natarajan; Srinivas Patil; Irith Pomeranz (DFT, 2006)

Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2006)

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. - Narendra Devta-Prasanna; Arun Gunda; P. Krishnamurthy; Sudhakar M. Reddy; Irith Pomeranz (ETS, 2006)

Fault Collapsing for Transition Faults Using Extended Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2006)

A delay fault model for at-speed fault simulation and test generation. - Irith Pomeranz; Sudhakar M. Reddy (ICCAD, 2006)

A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST. - Chaowen Yu; Sudhakar M. Reddy; Irith Pomeranz (IOLTS, 2006)

A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests. - Sungchul Park; Li Chen; Praveen Parvathala; Srinivas Patil; Irith Pomeranz (ITC, 2006)

Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 2006)

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. - Santiago Remersaro; Xijiang Lin; Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (ITC, 2006)

New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. - Gang Chen 011; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (VLSI Design, 2006)

The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2006)

A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. - Hangkyu Lee; Irith Pomeranz; Sudhakar M. Reddy (VTS, 2006)

Dominance Based Analysis for Large Volume Production Fail Diagnosis. - Bharath Seshadri; Irith Pomeranz; Srikanth Venkataraman; M. Enamul Amyeen; Sudhakar M. Reddy (VTS, 2006)

Scan Tests with Multiple Fault Activation Cycles for Delay Faults. - Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz; Xijiang Lin; Janusz Rajski (VTS, 2006)

On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (V&D@FLoC, 2006)

On Finding Don't Cares in Test Sequences for Sequential Circuits. - Yoshinobu Higami; Seiji Kajihara; Irith Pomeranz; Shin-ya Kobayashi; Yuzo Takamatsu (IEICE Trans. Inf. Syst., 2006)

On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2006)

Scan-BIST based on transition probabilities for circuits with single and multiple scan chains. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Generation of Functional Broadside Tests for Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Using Dummy Bridging Faults to Define Reduced Sets of Target Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Improved n-Detection Test Sequences Under Transparent Scan. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. - Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz (ASP-DAC, 2007)

Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation. - Irith Pomeranz; Praveen Parvathala; Srinivas Patil (ATS, 2007)

Diagnostic Test Generation Targeting Equivalence Classes. - Irith Pomeranz; Sudhakar M. Reddy (ATS, 2007)

Enhanced Broadside Testing for Improved Transition Fault Coverage. - Irith Pomeranz; Sudhakar M. Reddy (ATS, 2007)

On test generation by input cube avoidance. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2007)

A-Diagnosis: A Complement to Z-Diagnosis. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2007)

Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2007)

Diagnostic Test Generation Based on Subsets of Faults. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2007)

Testing for systematic defects based on DFM guidelines. - Dongok Kim; M. Enamul Amyeen; Srikanth Venkataraman; Irith Pomeranz; Swagato Basumallick; Berni Landau (ITC, 2007)

On the saturation of n-detection test sets with increased n. - Irith Pomeranz; Sudhakar M. Reddy (ITC, 2007)

Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2007)

Functional Broadside Tests with Different Levels of Reachability. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2007)

Low Shift and Capture Power Scan Tests. - Santiago Remersaro; Xijiang Lin; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (VLSI Design, 2007)

Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2007)

Scan-Based Tests with Low Switching Activity. - Santiago Remersaro; Xijiang Lin; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski (IEEE Des. Test Comput., 2007)

Worst-case and average-case analysis of n-detection test sets and test generation strategies. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2007)

Effectiveness of scan-based delay fault tests in diagnosis of transition faults. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2007)

Enhancing delay fault coverage through low-power segmented scan. - Zhuo Zhang 008; Sudhakar M. Reddy; Irith Pomeranz; Janusz Rajski; Bashir M. Al-Hashimi (IET Comput. Digit. Tech., 2007)

Invariant States and Redundant Logic in Synchronous Sequential Circuits. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs. - Irith Pomeranz; Sudhakar M. Reddy; Srikanth Venkataraman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Forming N-detection test sets without test generation. - Irith Pomeranz; Sudhakar M. Reddy (ACM Trans. Design Autom. Electr. Syst., 2007)

Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC, 2008)

Test vector chains for increased targeted and untargeted fault coverage. - Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC, 2008)

Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects. - Dongok Kim; Irith Pomeranz; M. Enamul Amyeen; Srikanth Venkataraman (ATS, 2008)

On tests to detect via opens in digital CMOS circuits. - Sudhakar M. Reddy; Irith Pomeranz; Chen Liu (DAC, 2008)

A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2008)

On Reducing Circuit Malfunctions Caused by Soft Errors. - Ilia Polian; Sudhakar M. Reddy; Irith Pomeranz; Xun Tang; Bernd Becker 001 (DFT, 2008)

ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. - Santiago Remersaro; Janusz Rajski; Thomas Rinderknecht; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2008)

Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2008)

Safe Fault Collapsing Based on Dominance Relations. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2008)

An Enhanced Logic BIST Architecture for Online Testing. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (IOLTS, 2008)

Detection of Internal Stuck-open Faults in Scan Chains. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2008)

Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2008)

Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2008)

On Common-Mode Skewed-Load and Broadside Tests. - Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (VLSI Design, 2008)

Synthesis for Broadside Testability of Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2008)

Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2008)

On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (VTS, 2008)

Functional Broadside Tests with Minimum and Maximum Switching Activity. - Irith Pomeranz; Sudhakar M. Reddy (J. Low Power Electron., 2008)

On Complete Functional Broadside Tests for Transition Faults. - Hangkyu Lee; Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

On the Saturation of n-Detection Test Generation by Different Definitions With Increased n. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Dynamic test compaction for a random test generation procedure with input cube avoidance. - Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC, 2009)

Detectability of internal bridging faults in scan chains. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (ASP-DAC, 2009)

N-distinguishing Tests for Enhanced Defect Diagnosis. - Gang Chen 011; Janusz Rajski; Sudhakar M. Reddy; Irith Pomeranz (Asian Test Symposium, 2009)

Fault Diagnosis under Transparent-Scan. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2009)

A scalable method for the generation of small test sets. - Santiago Remersaro; Janusz Rajski; Sudhakar M. Reddy; Irith Pomeranz (DATE, 2009)

On-chip Generation of the Second Primary Input Vectors of Broadside Tests. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2009)

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2009)

Improving the Detectability of Resistive Open Faults in Scan Cells. - Fan Yang 060; Sreejit Chakravarty; Narendra Devta-Prasanna; Sudhakar M. Reddy; Irith Pomeranz (DFT, 2009)

Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2009)

Partitioned n-detection test generation. - Irith Pomeranz; Sudhakar M. Reddy (ACM Great Lakes Symposium on VLSI, 2009)

Definition and application of approximate necessary assignments. - Irith Pomeranz; Sudhakar M. Reddy (ACM Great Lakes Symposium on VLSI, 2009)

State persistence: a property for guiding test generation. - Irith Pomeranz; Sudhakar M. Reddy (ACM Great Lakes Symposium on VLSI, 2009)

The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2009)

Definition and generation of partially-functional broadside tests. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2009)

Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2009)

Test vector chains for increasing the fault coverage and numbers of detections. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2009)

Test compaction methods for transition faults under transparent-scan. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2009)

Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Dependable Secur. Comput., 2009)

Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits. - Irith Pomeranz; Sudhakar M. Reddy (ACM Trans. Design Autom. Electr. Syst., 2009)

Random Test Generation With Input Cube Avoidance. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Functional and partially-functional skewed-load tests. - Irith Pomeranz; Sudhakar M. Reddy (ASP-DAC, 2010)

On Bias in Transition Coverage of Test Sets for Path Delay Faults. - Irith Pomeranz; Sudhakar M. Reddy (Asian Test Symposium, 2010)

Reducing the storage requirements of a test sequence by using a background vector. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2010)

On reset based functional broadside tests. - Irith Pomeranz; Sudhakar M. Reddy (DATE, 2010)

Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs. - Irith Pomeranz; Sudhakar M. Reddy (DFT, 2010)

Input test data volume reduction based on test vector chains. - Irith Pomeranz; Sudhakar M. Reddy (ETS, 2010)

Deterministic broadside test generation for transition path delay faults. - Bo Yao 002; Irith Pomeranz; Sudhakar M. Reddy (ACM Great Lakes Symposium on VLSI, 2010)

Selecting state variables for improved on-line testability through output response comparison of identical circuits. - Irith Pomeranz; Sudhakar M. Reddy (IOLTS, 2010)

Multiple fault activation cycle tests for transistor stuck-open faults. - Narendra Devta-Prasanna; Arun Gunda; Sudhakar M. Reddy; Irith Pomeranz (ITC, 2010)

Output-Dependent Diagnostic Test Generation. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2010)

Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. - Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 2010)

Defect diagnosis based on DFM guidelines. - Dongok Kim; Irith Pomeranz; M. Enamul Amyeen; Srikanth Venkataraman (VTS, 2010)

Forming multi-cycle tests for delay faults by concatenating broadside tests. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2010)

On multiple bridging faults. - Irith Pomeranz; Sudhakar M. Reddy (VTS, 2010)

Diagnosis of path delay faults based on low-coverage tests. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2010)

Static test compaction for diagnostic test sets of full-scan circuits. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2010)

Test Sequences with Reduced and Increased Switching Activity. - Irith Pomeranz; Sudhakar M. Reddy (J. Low Power Electron., 2010)

Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Computers, 2010)

TOV: Sequential Test Generation by Ordering of Test Vectors. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

On Test Generation With Test Vector Improvement. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

On Undetectable Faults and Fault Diagnosis. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Path Selection for Transition Path Delay Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Robust Fault Models Where Undetectable Faults Imply Logic Redundancy. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Switching Activity as a Test Compaction Heuristic for Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Selection of a Fault Model for Fault Diagnosis Based on Unique Responses. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Fault diagnosis aware ATE assisted test response compaction. - J. M. Howard; Sudhakar M. Reddy; Irith Pomeranz; Bernd Becker 001 (ASP-DAC, 2011)

Diagnosis of transition fault clusters. - Irith Pomeranz (DAC, 2011)

Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. - Amit Kumar 004; Sudhakar M. Reddy; Irith Pomeranz; Bernd Becker 001 (DATE, 2011)

Built-in generation of functional broadside tests. - Irith Pomeranz (DATE, 2011)

Max-Fill: A method to generate high quality delay tests. - Xiaoxin Fan; Sudhakar M. Reddy; Irith Pomeranz (DDECS, 2011)

On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests. - Irith Pomeranz (ETS, 2011)

Augmenting Functional Broadside Tests for Transition Fault Coverage with Bounded Switching Activity. - Irith Pomeranz (PRDC, 2011)

Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets for Transition Faults. - Irith Pomeranz (PRDC, 2011)

Static test compaction for delay fault test sets consisting of broadside and skewed-load tests. - Irith Pomeranz (VTS, 2011)

On clustering of undetectable transition faults in standard-scan circuits. - Irith Pomeranz (VTS, 2011)

Primary input cones based on test sequences in synchronous sequential circuits. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2011)

Two-dimensional partially functional broadside tests. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2011)

Sizes of test sets for path delay faults using strong and weak non-robust tests. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2011)

Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2011)

Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan. - Irith Pomeranz; Sudhakar M. Reddy (J. Low Power Electron., 2011)

Generation of Multi-Cycle Broadside Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Scan Shift Power of Functional Broadside Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Subsets of Primary Input Vectors in Sequential Test Generation for Single Stuck-at Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Reducing the switching activity of test sequences under transparent-scan. - Irith Pomeranz; Sudhakar M. Reddy (ACM Trans. Design Autom. Electr. Syst., 2011)

Fixed-State Tests for Delay Faults in Scan Designs. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

On Functional Broadside Tests With Functional Propagation Conditions. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Broadside and Functional Broadside Tests for Partial-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Static Test Data Volume Reduction Using Complementation or Modulo- M Addition. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faults. - Irith Pomeranz (DFT, 2012)

Built-in generation of multi-cycle broadside tests. - Irith Pomeranz (DFT, 2012)

Maintaining proximity to functional operation conditions under enhanced-scan tests based on functional broadside tests. - Irith Pomeranz (DFT, 2012)

On the detection of path delay faults by functional broadside tests. - Irith Pomeranz (ETS, 2012)

Performance aware partitioning for 3D-SOCs. - Amit Kumar 004; Sudhakar M. Reddy; Bernd Becker 001; Irith Pomeranz (ISOCC, 2012)

TSV and DFT cost aware circuit partitioning for 3D-SOCs. - Amit Kumar 004; Sudhakar M. Reddy; Irith Pomeranz; Bernd Becker 001 (ISQED, 2012)

Static test compaction for transition faults under the hazard-based detection conditions. - Irith Pomeranz (VTS, 2012)

Test vector chains for increased resolution and reduced storage of diagnostic tests. - Irith Pomeranz (IET Comput. Digit. Tech., 2012)

Undetectable transition faults under broadside tests with constant primary input vectors. - Irith Pomeranz (IET Comput. Digit. Tech., 2012)

Functional broadside tests for embedded logic blocks. - Irith Pomeranz (IET Comput. Digit. Tech., 2012)

Reset and partial-reset-based functional broadside tests. - Irith Pomeranz; Sudhakar M. Reddy (IET Comput. Digit. Tech., 2012)

On the Computation of Common Test Data for Broadside and Skewed-Load Tests. - Irith Pomeranz (IEEE Trans. Computers, 2012)

Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length. - Irith Pomeranz (IEEE Trans. Computers, 2012)

Fast Identification of Undetectable Transition Faults under Functional Broadside Tests. - Irith Pomeranz (IEEE Trans. Computers, 2012)

On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests. - Irith Pomeranz (IEEE Trans. Computers, 2012)

Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

A Metric for Identifying Detectable Path Delay Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Generation of Mixed Test Sets for Transition Faults. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Non-Uniform Coverage by n -Detection Test Sets. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Resolution of Diagnosis Based on Transition Faults. - Irith Pomeranz; Sudhakar M. Reddy (IEEE Trans. Very Large Scale Integr. Syst., 2012)

On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes. - Irith Pomeranz (DATE, 2013)

Classes of difficult-to-diagnose transition fault clusters. - Irith Pomeranz (DFTS, 2013)

Generation of compact multi-cycle diagnostic test sets. - Irith Pomeranz (ETS, 2013)

Path selection based on static timing analysis considering input necessary assignments. - Bo Yao 002; Arani Sinha; Irith Pomeranz (VTS, 2013)

Static test compaction for mixed broadside and skewed-load transition fault test sets. - Irith Pomeranz (IET Comput. Digit. Tech., 2013)

On multi-cycle test cubes. - Irith Pomeranz (IET Comput. Digit. Tech., 2013)

Low-power test sets under test-related primary input constraints. - Irith Pomeranz (Int. J. Crit. Comput. Based Syst., 2013)

Diagnostic Test Sets with Increased Switching Activity for Transition Faults. - Irith Pomeranz (J. Low Power Electron., 2013)

An Adjacent Switching Activity Metric under Functional Broadside Tests. - Irith Pomeranz (IEEE Trans. Computers, 2013)

Signal-Transition Patterns of Functional Broadside Tests. - Irith Pomeranz (IEEE Trans. Computers, 2013)

Generation of Functional Broadside Tests for Logic Blocks With Constrained Primary Input Sequences. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Functional Broadside Tests With Incompletely Specified Scan-In States. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Non-Test Cubes for Test Generation Targeting Hard-to-Detect Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Built-in generation of multicycle functional broadside tests with observation points. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2013)

Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Computing Two-Pattern Test Cubes for Transition Path Delay Faults. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Broadside and Skewed-Load Tests Under Primary Input Constraints. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2013)

On Test Compaction of Broadside and Skewed-Load Test Cubes. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Functional Broadside Templates for Low-Power Test Generation. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Test and non-test cubes for diagnostic test generation based on merging of test cubes. - Irith Pomeranz (DATE, 2014)

Substituting transition faults with path delay faults as a basic delay fault model. - Irith Pomeranz (DATE, 2014)

A distance-based test cube merging procedure for compatible and incompatible test cubes. - Irith Pomeranz (ETS, 2014)

Built-in generation of functional broadside tests considering primary input constraints. - Bo Yao 002; Irith Pomeranz; Srikanth Venkataraman; M. Enamul Amyeen (ACM Great Lakes Symposium on VLSI, 2014)

FDPIC: Generation of Functional Test Sequences Based on Fault-Dependent Primary Input Cubes. - Irith Pomeranz (ISVLSI, 2014)

OBO: An Output-by-Output Scoring Algorithm for Fault Diagnosis. - Irith Pomeranz (ISVLSI, 2014)

Innovative practices session 10C: Advances in DFT and compression. - Rohit Kapur; Irith Pomeranz (VTS, 2014)

Fault simulation with test switching for static test compaction. - Irith Pomeranz (VTS, 2014)

On the use of multi-cycle tests for storage of two-cycle broadside tests. - Irith Pomeranz (VTS, 2014)

Reducing the input test data volume under transparent scan. - Irith Pomeranz (IET Comput. Digit. Tech., 2014)

Multi-cycle broadside tests with runs of constant primary input vectors. - Irith Pomeranz (IET Comput. Digit. Tech., 2014)

Sharing Logic for Built-In Generationof Functional Broadside Tests. - Irith Pomeranz (IEEE Trans. Computers, 2014)

Unknown Output Values of Faulty Circuits and Output Response Compaction. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Selection of Functional Test Sequences With Overlaps. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Simultaneous Generation of Functional and Low-Power Non-Functional Broadside Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Functional Broadside Tests for Multistep Defect Diagnosis. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Improving the Accuracy of Defect Diagnosis by Considering Fewer Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Low-power skewed-load tests based on functional broadside tests. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2014)

Design-for-testability for multi-cycle broadside tests by holding of state variables. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2014)

Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Low-Power Test Generation by Merging of Functional Broadside Test Cubes. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Low-Power Diagnostic Test Sets for Transition Faults Based on Functional Broadside Tests. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Generation of close-to-functional broadside tests with equal primary input vectors. - Irith Pomeranz (DAC, 2015)

Piecewise-functional broadside tests based on intersections of reachable states. - Irith Pomeranz (DFTS, 2015)

On test program compaction. - Marco Gaudesi; Matteo Sonza Reorda; Irith Pomeranz (ETS, 2015)

FaultHound: value-locality-based soft-fault tolerance. - Nitin 002; Irith Pomeranz; T. N. Vijaykumar (ISCA, 2015)

Reducing the Storage Requirements of a Set of Functional Test Sequences by Using a Background Sequence. - Irith Pomeranz (ISVLSI, 2015)

Improving the accuracy of defect diagnosis by considering reduced diagnostic information. - Irith Pomeranz (VTS, 2015)

Test vector omission with minimal sets of simulated faults. - Irith Pomeranz (VTS, 2015)

Test compaction by test cube merging for four-way bridging faults. - Irith Pomeranz (VTS, 2015)

A definition of the number of detections for faults with single tests in a compact scan-based test set. - Irith Pomeranz (VTS, 2015)

Use of input necessary assignments for test generation based on merging of test cubes. - Irith Pomeranz (IET Comput. Digit. Tech., 2015)

Piecewise-Functional Broadside Tests Based on Reachable States. - Irith Pomeranz (IEEE Trans. Computers, 2015)

Two-Dimensional Static Test Compaction for Functional Test Sequences. - Irith Pomeranz (IEEE Trans. Computers, 2015)

Test Vector Omission for Fault Coverage Improvement of Functional Test Sequences. - Irith Pomeranz (IEEE Trans. Computers, 2015)

A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Computation of Seeds for LFSR-Based Diagnostic Test Generation. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2015)

FOLD: Extreme Static Test Compaction by Folding of Functional Test Sequences. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2015)

Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2015)

Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Static Test Compaction for Low-Power Test Sets by Increasing the Switching Activity. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Modeling a Set of Functional Test Sequences as a Single Sequence for Test Compaction. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Test Compaction by Sharing of Functional Test Sequences Among Logic Blocks. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction. - M. Enamul Amyeen; Irith Pomeranz; Srikanth Venkataraman (ATS, 2016)

On the Switching Activity in Faulty Circuits During Test Application. - Irith Pomeranz; Sudhakar M. Reddy (ATS, 2016)

A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test Set. - Irith Pomeranz (ISVLSI, 2016)

Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm. - Shraddha Bodhe; M. Enamul Amyeen; Clariza Galendez; Houston Mooers; Irith Pomeranz; Srikanth Venkataraman (VTS, 2016)

A convergent procedure for partially-reachable states. - Irith Pomeranz (VTS, 2016)

Static test compaction for circuits with multiple independent scan chains. - Irith Pomeranz (IET Comput. Digit. Tech., 2016)

Improving the accuracy of defect diagnosis by adding and removing tests. - Irith Pomeranz (IET Comput. Digit. Tech., 2016)

Combined input test data volume reduction for mixed broadside and skewed-load test sets. - Irith Pomeranz (IET Comput. Digit. Tech., 2016)

Improving the Accuracy of Defect Diagnosis with Multiple Sets of Candidate Faults. - Irith Pomeranz (IEEE Trans. Computers, 2016)

LFSR-Based Generation of Partially-Functional Broadside Tests. - Irith Pomeranz (IEEE Trans. Computers, 2016)

Balancing the Numbers of Detected Faults for Improved Test Set Quality. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching Activity. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Design-for-Testability for Functional Broadside Tests under Primary Input Constraints. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2016)

N-Detection Test Sets for Circuits with Multiple Independent Scan Chains. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2016)

Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2016)

Diagnostic Fail Data Minimization Using an N-Cover Algorithm. - Shraddha Bodhe; M. Enamul Amyeen; Irith Pomeranz; Srikanth Venkataraman (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Computing Seeds for LFSR-Based Test Generation From Nontest Cubes. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Test Compaction with Dynamic Updating of Faults for Coverage of Undetected Transition Fault Sites. - Irith Pomeranz (ATS, 2017)

Compaction of a Transparent-Scan Sequence to Reduce the Fail Data Volume for Scan Chain Faults. - Irith Pomeranz (ATS, 2017)

A bridging fault model for line coverage in the presence of undetected transition faults. - Irith Pomeranz (DATE, 2017)

Static Compaction by Merging of Seeds for LFSR-Based Test Generation. - Irith Pomeranz (ISVLSI, 2017)

Functional Broadside Test Generation Using a Commercial ATPG Tool. - Naixing Wang; Bo Yao 002; Xijiang Lin; Irith Pomeranz (ISVLSI, 2017)

Selecting target bridging faults for uniform circuit coverage. - Irith Pomeranz (ITC, 2017)

POSTT: Path-oriented static test compaction for transition faults in scan circuits. - Irith Pomeranz (ITC, 2017)

Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure. - Srikanth Venkataraman; Irith Pomeranz; Shraddha Bodhe; M. Enamul Amyeen (ITC, 2017)

Fail data reduction for diagnosis of scan chain faults under transparent-scan. - Irith Pomeranz (VTS, 2017)

Using piecewise-functional broadside tests for functional broadside test compaction. - Irith Pomeranz (VTS, 2017)

Reconstruction of a functional test sequence for increased fault coverage. - Irith Pomeranz (IET Comput. Digit. Tech., 2017)

Metric for the ability of functional capture cycles to ensure functional operation conditions. - Irith Pomeranz (IET Comput. Digit. Tech., 2017)

New Techniques to Reduce the Execution Time of Functional Test Programs. - Marco Gaudesi; Irith Pomeranz; Matteo Sonza Reorda; Giovanni Squillero (IEEE Trans. Computers, 2017)

Sequential Test Generation Based on Preferred Primary Input Cubes. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

LFSR-Based Generation of Multicycle Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Identifying Biases of a Defect Diagnosis Procedure. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Restoration-Based Merging of Functional Test Sequences. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Close-to-Functional Broadside Tests With a Safety Margin. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Computation of Seeds for LFSR-Based n-Detection Test Generation. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2017)

Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2017)

Test Modification for Reduced Volumes of Fail Data. - Irith Pomeranz; M. Enamul Amyeen; Srikanth Venkataraman (ACM Trans. Design Autom. Electr. Syst., 2017)

Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction. - Shraddha Bodhe; Irith Pomeranz; M. Enamul Amyeen; Srikanth Venkataraman (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Selecting Replacements for Undetectable Path Delay Faults. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set. - Irith Pomeranz (DFT, 2018)

Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests. - Naixing Wang; Irith Pomeranz; Brady Benware; M. Enamul Amyeen; Srikanth Venkataraman (DFT, 2018)

Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests. - Irith Pomeranz (ETS, 2018)

Interconnect-aware tests to complement gate-exhaustive tests. - Irith Pomeranz; Srikanth Venkataraman (ETS, 2018)

On Close-to-Functional Test Sequences. - Irith Pomeranz (ITC, 2018)

On-chip generation of primary input sequences for multicycle functional broadside tests. - Irith Pomeranz (IET Comput. Digit. Tech., 2018)

Static test compaction procedure for large pools of multicycle functional broadside tests. - Irith Pomeranz (IET Comput. Digit. Tech., 2018)

Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation Points. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

An Initialization Process to Support Online Testing Based on Output Comparison for Identical Finite-State Machines. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside Tests. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2018)

Dynamically Determined Preferred Values and a Design-for-Testability Approach for Multiplexer Select Inputs under Functional Test Sequences. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2018)

Selecting Functional Test Sequences for Defect Diagnosis. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Observation Points on State Variables for the Compaction of Multicycle Tests. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2018)

TEA: A Test Generation Algorithm for Designs with Timing Exceptions. - Naixing Wang; Chen Wang 014; Kun-Han Tsai; Wu-Tung Cheng; Xijiang Lin; Mark Kassab; Irith Pomeranz (ATS, 2019)

Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. - Naixing Wang; Irith Pomeranz; Sudhakar M. Reddy; Arani Sinha; Srikanth Venkataraman (DATE, 2019)

Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults. - Irith Pomeranz (ITC, 2019)

Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation. - Irith Pomeranz (ITC, 2019)

Test Compaction Under Bounded Transparent-Scan. - Irith Pomeranz (VTS, 2019)

Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults. - Irith Pomeranz; Vivek Chickermane; Srikanth Venkataraman (VTS, 2019)

Updating the sets of target faults during test generation for multiple fault models. - Irith Pomeranz (IET Comput. Digit. Tech., 2019)

Diagnostic Test Generation That Addresses Diagnostic Holes. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

LFSR-Based Test Generation for Path Delay Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Skewed-Load Tests for Transition and Stuck-at Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Boundary-Functional Broadside and Skewed-Load Tests. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2019)

Incomplete Tests for Undetectable Faults to Improve Test Set Quality. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2019)

Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. - Naixing Wang; Irith Pomeranz; Sudhakar M. Reddy; Arani Sinha; Srikanth Venkataraman (ACM Trans. Design Autom. Electr. Syst., 2019)

Test Compaction by Test Removal Under Transparent Scan. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Extended Transparent-Scan. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Padding of Multicycle Broadside and Skewed-Load Tests. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Improving a Test Set to Cover Test Holes by Detecting Gate-Exhaustive Faults. - Irith Pomeranz (DFT, 2020)

Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside Tests. - Irith Pomeranz (IOLTS, 2020)

Reduced Fault Coverage as a Target for Design Scaffolding Security. - Irith Pomeranz; Sandip Kundu (IOLTS, 2020)

Selecting Close-to-Functional Path Delay Faults for Test Generation. - Irith Pomeranz (ITC, 2020)

Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs. - Irith Pomeranz (VTS, 2020)

Non-Masking Non-Robust Tests for Path Delay Faults. - Irith Pomeranz (VTS, 2020)

LFSR-based generation of boundary-functional broadside tests. - Irith Pomeranz (IET Comput. Digit. Tech., 2020)

Multicycle Broadside and Skewed-Load Tests for Test Compaction. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Reverse Low-Power Broadside Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Switching Activity of Faulty Circuits in Presence of Multiple Transition Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Broadside Tests for Transition and Stuck-At Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Globally Functional Transparent-Scan Sequences. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

New Targets for Diagnostic Test Generation. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Functional Broadside Tests Under Broadcast Scan. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Direct Computation of LFSR-Based Stored Tests for Broadside and Skewed-Load Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

LFSR-Based Test Generation for Reduced Fail Data Volume. - Irith Pomeranz; Srikanth Venkataraman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Target Faults for Test Compaction Based on Multicycle Tests. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2020)

Selection of Primary Output Vectors to Observe Under Multicycle Tests. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2020)

RETRO: Reintroducing Tests for Improved Reverse Order Fault Simulation. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Broad-Brush Compaction for Sequential Test Generation. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Positive and Negative Extra Clocking of LFSR Seeds for Reduced Numbers of Stored Tests. - Irith Pomeranz (ATS, 2021)

Zoom-In Feature for Storage-Based Logic Built-In Self-Test. - Irith Pomeranz (DFT, 2021)

Compact Set of LFSR Seeds for Diagnostic Tests. - Irith Pomeranz (VTS, 2021)

Maximal Independent Fault Set for Gate-Exhaustive Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

PRESERVE: Static Test Compaction that Preserves Individual Numbers of Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Padding of LFSR Seeds for Reduced Input Test Data Volume. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Storage-Based Built-In Self-Test for Gate-Exhaustive Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume. - Irith Pomeranz; M. Enamul Amyeen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Covering Test Holes of Functional Broadside Tests. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2021)

Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2021)

Logic Diagnosis with Hybrid Fail Data. - Irith Pomeranz; M. Enamul Amyeen (ACM Trans. Design Autom. Electr. Syst., 2021)

Partitioning Functional Test Sequences Into Multicycle Functional Broadside Tests. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Test Compaction by Backward and Forward Extension of Multicycle Tests. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults. - Irith Pomeranz; Xijiang Lin (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. - Hari Addepalli; Irith Pomeranz; M. Enamul Amyeen; Suriyaprakash Natarajan; Arani Sinha; Srikanth Venkataraman (ATS, 2022)

Two-Dimensional Test Generation Objective. - Irith Pomeranz (ATS, 2022)

Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines. - Irith Pomeranz (ATS, 2022)

Usable Circuits with Imperfect Scan Logic. - Irith Pomeranz (ATS, 2022)

Storage-Based Logic Built-In Self-Test with Variable-Length Test Data. - Irith Pomeranz (DFT, 2022)

Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied Tests. - Hari Addepalli; Irith Pomeranz (ACM Great Lakes Symposium on VLSI, 2022)

Compaction of Compressed Bounded Transparent-Scan Test Sets. - Irith Pomeranz (ACM Great Lakes Symposium on VLSI, 2022)

Test Generation for an Iterative Design Flow with RTL Changes. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (ITC, 2022)

Transforming an $n$-Detection Test Set into a Test Set for a Variety of Fault Models. - Irith Pomeranz (ITC, 2022)

Fast Test Generation for Structurally Similar Circuits. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (VTS, 2022)

Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Static Test Compaction Using Independent Suffixes of a Transparent-Scan Sequence. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Multicycle Tests With Fault Detection Test Data for Improved Logic Diagnosis. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Storage-Based Logic Built-in Self-Test With Multicycle Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Increasing the Fault Coverage of a Truncated Test Set. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2022)

Preponing Fault Detections for Test Compaction Under Transparent Scan. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Test Sequences for Faults in the Scan Logic. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation Lines. - Irith Pomeranz (ITC, 2023)

Fully Deterministic Storage Based Logic Built-In Self-Test. - Subashini Gopalsamy; Irith Pomeranz (VTS, 2023)

Expanding a Pool of Functional Test Sequences to Support Test Compaction. - Irith Pomeranz (VTS, 2023)

Compact Set of Functional Broadside Tests with Fault Detection on Primary Outputs. - Irith Pomeranz (VTS, 2023)

Storage and Counter Based Logic Built-In Self-Test. - Irith Pomeranz (IEEE Access, 2023)

Topping Off Test Sets Under Bounded Transparent Scan. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Estimating the Number of Extra Tests During Iterative Test Generation for Single-Cycle Gate-Exhaustive Faults. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Path Unselection for Path Delay Fault Test Generation. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Diagnostic Test Point Insertion and Test Compaction. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Sharing of Compressed Tests Among Logic Blocks. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Test Data Compression for Transparent-Scan Sequences. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Storage-Based Logic Built-In Self-Test With Cyclic Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Partially Specified Output Response for Reduced Fail Data Volume. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Generating Storage-Aware Test Sets Targeting Several Fault Models. - Hari Addepalli; Irith Pomeranz; M. Enamul Amyeen; Suriyaprakash Natarajan; Arani Sinha; Srikanth Venkataraman (ISVLSI, 2024)

Delay Monitoring Under Different PVT Corners for Test and Functional Operation. - Hari Addepalli; Jiezhong Wu; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (ITC, 2024)

Functionally-Possible Gate-Exhaustive Bridging Faults. - Irith Pomeranz (ITC, 2024)

A Storage Based LBIST Scheme for Logic Diagnosis. - Subashini Gopalsamy; Irith Pomeranz (VTS, 2024)

Test Compaction Using (k, 1)-Cycle Tests. - Irith Pomeranz (VTS, 2024)

Longest Path Selection Based on Path Identifiers. - Irith Pomeranz (IEEE Access, 2024)

Sharing of Topped-Off Compressed Test Sets Among Logic Blocks. - Irith Pomeranz (IEEE Access, 2024)

Functional Compaction for Functional Test Sequences. - Irith Pomeranz (IEEE Access, 2024)

Weak and Strong Non-Robust Tests for Functionally Possible Path Delay Faults. - Irith Pomeranz (IEEE Access, 2024)

Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Testability Evaluation for Local Design Modifications. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Generation of Two-Cycle Tests for Structurally Similar Circuits. - Jerin Joe; Nilanjan Mukherjee 001; Irith Pomeranz; Janusz Rajski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Test Insertion for Dynamic Test Compaction. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Reduced On-chip Storage of Seeds for Built-in Test Generation. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2024)

Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2024)

Conventional Tests for Approximate Scan Logic. - Irith Pomeranz (IEEE Des. Test, 2024)

Functionally Possible Path Delay Faults With High Functional Switching Activity. - Irith Pomeranz; Yervant Zorian (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Test Generation for Functionally Possible Subpaths. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Functional Design-for-Testability for Functional Test Sequences. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Unconstrained-Activation Functional-Detection Scan-Based Tests. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Chip Aging and Double Transition Faults. - Irith Pomeranz (VTS, 2025)

Fine-Grained Steepening of the Fault Coverage Curve of a Pool of Functional Test Sequences. - Irith Pomeranz (VTS, 2025)

Timing-Verification Test Generation Targeting Small Delay Defects. - Jiezhong Wu; Nilanjan Mukherjee 001; Irith Pomeranz; Kun-Han Tsai; Janusz Rajski (VTS, 2025)

Arranging a Pool of Functional Test Sequences for Variable In-Field Test Periods. - Irith Pomeranz (IEEE Access, 2025)

Functionally-Possible Subcircuit-Based Tests for Path Delay Faults. - Irith Pomeranz (IEEE Access, 2025)

DYCOCO: Dynamic Configuration-Based Test Compaction. - Irith Pomeranz (IEEE Access, 2025)

SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2025)

Direct Search Procedure for Functional Compaction With Improved Fault Coverage. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

COCO: Configuration-Based Compaction of a Compressed Topped-Off Test Set. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Test Templates to Guide Test Generation for Single-Cycle Gate-Exhaustive Faults. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2025)

Retry-Based Synchronization for Online Testing of Identical Logic Blocks. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2025)

DTGx2: Dual Target Diagnostic Test Generation. - Irith Pomeranz (ACM Trans. Design Autom. Electr. Syst., 2025)

Chip Aging and Transition Faults With High Switching Activities Under Scan-Based Tests. - Irith Pomeranz (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Varying Periods of In-Field Testing With Storage- and Counter-Based Logic Built-In Self-Test. - Irith Pomeranz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)