Resistive memory device requirements for a neural algorithm accelerator. - Sapan Agarwal; Steven J. Plimpton; David R. Hughart; Alexander H. Hsia; Isaac Richter; Jonathan A. Cox; Conrad D. James; Matthew J. Marinella (IJCNN, 2016)

Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator. - Matthew J. Marinella; Sapan Agarwal; Alexander H. Hsia; Isaac Richter; Robin Jacobs-Gedrim; John Niroula; Steven J. Plimpton; Engin Ipek; Conrad D. James (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

DeTRAP: RISC-V Return Address Protection With Debug Triggers. - Isaac Richter; Jie Zhou; John Criswell (SecDev, 2024)