A 29-ns 64-Mb DRAM with hierarchical array architecture. - Masayuki Nakamura; Tugio Takahashi; Takesada Akiba; Goro Kitsukawa; Makoto Morino; Toshihiro Sekiguchi; Isamu Asano; Katsuo Komatsuzaki; Yoshitaka Tadaki; Songsu Cho; Kazuhiko Kajigaya; Tadashi Tachibana; et al. (IEEE J. Solid State Circuits, 1996)

A novel on-chip voltage generator for low voltage DRAMs and PRAMs. - Tatsuya Matano; Koji Sato; Kiyoshi Nakai; Isamu Asano (CICC, 2009)

Materials Engineering for High Performance Ferroelectric Memory. - Ashonita Chavan; Adharsh Rajagopal; Yixin Yan; Isamu Asano; Devanarayanan Ettisserry; Vassil Antonov; Giorgio Servalli; Alessandro Calderoni; Nirmal Ramaswamy (IMW, 2024)