A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. - Tatsuya Matano; Yasuhiro Takai; Tsugio Takahashi; Yuusuke Sakito; Isamu Fujii; Yoshihiro Takaishi; Hiroki Fujisawa; Shuichi Kubouchi; Seiji Narui; Koji Arai; Makoto Morino; Masayuki Nakamura; et al. (IEEE J. Solid State Circuits, 2003)

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. - Hiroki Fujisawa; Masayuki Nakamura; Yasuhiro Takai; Yasuji Koshikawa; Tatsuya Matano; Seiji Narui; Narikazu Usuki; Chiaki Dono; Shinichi Miyatake; Makoto Morino; Koji Arai; Shuichi Kubouchi; et al. (IEEE J. Solid State Circuits, 2005)

An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme. - Hiroki Fujisawa; Shuichi Kubouchi; Koji Kuroki; Naohisa Nishioka; Yoshiro Riho; Hiromasa Noda; Isamu Fujii; Hideyuki Yoko; Ryuuji Takishita; Takahiro Ito; Hitoshi Tanaka; Masayuki Nakamura (ISSCC, 2006)

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme. - Hiroki Fujisawa; Shuichi Kubouchi; Koji Kuroki; Naohisa Nishioka; Yoshiro Riho; Hiromasa Noda; Isamu Fujii; Hideyuki Yoko; Ryuuji Takishita; Takahiro Ito; Hitoshi Tanaka; Masayuki Nakamura (IEEE J. Solid State Circuits, 2007)