A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture. - Harufusa Kondoh; Hiromi Notani; Hideaki Yamanaka; Keiichi Higashitani; Hirotaka Saito; Isamu Hayashi; Shigeki Kohama; Yoshio Matsuda; Kazuyoshi Oshima; Masao Nakaya (IEEE J. Solid State Circuits, 1993)

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. - Fukashi Morishita; Isamu Hayashi; Hideto Matsuoka; Kazuhiro Takahashi; Kuniyasu Shigeta; Takayuki Gyohten; Mitsutaka Niiro; Hideyuki Noda; Mako Okamoto; Atsushi Hachisuka; Atsushi Amo; Hiroki Shinkawata; et al. (IEEE J. Solid State Circuits, 2005)

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. - Hideyuki Noda; Kazunari Inoue; Masayuki Kuroiwa; Futoshi Igaue; Kouji Yamamoto 002; Hans Jürgen Mattausch; Tetsushi Koide; Atsushi Amo; Atsushi Hachisuka; Shinya Soeda; Isamu Hayashi; Fukashi Morishita; et al. (IEEE J. Solid State Circuits, 2005)

A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. - Kazutami Arimoto; Fukashi Morishita; Isamu Hayashi; Tetsushi Tanizaki; Takashi Ipposhi; Katsumi Dosaka (CICC, 2006)

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. - Takayuki Gyohten; Fukashi Morishita; Isamu Hayashi; Mako Okamoto; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Yasutaka Horiba (IEICE Trans. Electron., 2006)

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. - Fukashi Morishita; Hideyuki Noda; Isamu Hayashi; Takayuki Gyohten; Mako Okamoto; Takashi Ipposhi; Shigeto Maegawa; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2007)

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. - Kazutami Arimoto; Fukashi Morishita; Isamu Hayashi; Katsumi Dosaka; Hiroki Shimano; Takashi Ipposhi (IEEE J. Solid State Circuits, 2007)

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. - Fukashi Morishita; Isamu Hayashi; Takayuki Gyohten; Hideyuki Noda; Takashi Ipposhi; Hiroki Shimano; Katsumi Dosaka; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit. - Abul Hasan Johari; Satoshi Kumaki; Takeshi Matsubara; Isamu Hayashi; Hiroki Ishikuro (APCCAS, 2010)

A 0.5V 6-bit scalable phase interpolator. - Satoshi Kumaki; Abul Hasan Johari; Takeshi Matsubara; Isamu Hayashi; Hiroki Ishikuro (APCCAS, 2010)

A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS. - Takeshi Matsubara; Isamu Hayashi; Abul Hasan Johari; Tadahiro Kuroda; Hiroki Ishikuro (RWS, 2012)

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. - Isamu Hayashi; Teruhiko Amano; Naoya Watanabe; Yuji Yano; Yasuto Kuroda; M. Shirata; Katsumi Dosaka; Koji Nii; Hideyuki Noda; Hiroyuki Kawai (IEEE J. Solid State Circuits, 2013)

13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM. - Koji Nii; Teruhiko Amano; Naoya Watanabe; Minoru Yamawaki; Kenji Yoshinaga; Mihoko Wada; Isamu Hayashi (ISSCC, 2014)