A 30-ns 256-Mb DRAM with a multidivided array structure. - Tadahiko Sugibayashi; Toshio Takeshima; Isao Naritake; Tatsuya Matano; Hiroshi Takada; Yoshiharu Aimoto; Koichiro Furuta; Mamoru Fujita; Takanori Saeki; Hiroshi Sugawara; Tatsunori Murotani; Naoki Kasai; et al. (IEEE J. Solid State Circuits, 1993)

A 1-Gb DRAM for file applications. - Tadahiko Sugibayashi; Isao Naritake; Satoshi Utsugi; Kentaro Shibahara; Ryuichi Oikawa; Hidemitsu Mori; Shouichi Iwao; Tatsunori Murotani; Kuniaki Koyama; Shinichi Fukuzawa; Toshiro Itani; Kunihiko Kasama; et al. (IEEE J. Solid State Circuits, 1995)

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor. - Takashi Okuda; Isao Naritake; Tadahiko Sugibayashi; Yuji Nakajima; Tatsunori Murotani (IEEE J. Solid State Circuits, 2000)