A New Algorithm for Generating All the Maximal Independent Sets. - Shuji Tsukiyama; Mikio Ide; Hiromu Ariyoshi; Isao Shirakawa (SIAM J. Comput., 1977)

An approach to gate assignment and module placement for printed wiring boards. - Ikuo Nishioka; Takuji Kurimoto; Seiji Yamamoto; Isao Shirakawa; Hiroshi Ozaki (DAC, 1978)

A layout system for the random logic portion of MOS LSI. - Isao Shirakawa; Noboru Okuda; Takashi Harada; Sadahiro Tani; Hiroshi Ozaki (DAC, 1980)

An Algorithm to Enumerate All Cutsets of a Graph in Linear Time per Cutset. - Shuji Tsukiyama; Isao Shirakawa; Hiroshi Ozaki; Hiromu Ariyoshi (J. ACM, 1980)

Some comments on permutation layout. - Isao Shirakawa (Networks, 1980)

An Approach to Gate Assignment and Module Placement for Printed Wiring Boards. - Ikuo Nishioka; Takuji Kurimoto; Seiji Yamamoto; Toru Chiba; Isao Shirakawa; Hiroshi Ozaki (IEEE Trans. Computers, 1980)

A Layout System for the Random Logic Portion of an MOS LSI Chip. - Isao Shirakawa; Noboru Okuda; Takashi Harada; Sadahiro Tani; Hiroshi Ozaki (IEEE Trans. Computers, 1981)

LINKS-1: A Parallel Pipelined Multimicrocomputer System for Image Creation - Hitoshi Nishimura; Hiroshi Ohno; Toru Kawata; Isao Shirakawa; Koichi Omura (ISCA, 1983)

A Rerouting Scheme for Single-Layer Printed Wiring Boards. - Isao Shirakawa; Shin Futagami (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

A New Global Router for Gate Array LSIsi. - Shuji Tsukiyama; Ikuo Harada; Masahiro Fukui; Isao Shirakawa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

On the Layering Problem of Multilayer PWB Wiring. - Shuji Tsukiyama; Ernest S. Kuh; Isao Shirakawa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

A tree-structured parallel processing system for image generation by ray tracing. - Hiroshi Deguchi; Isao Shirakawa; Koichi Omura; Masato Nishida; Hitoshi Nishimura; Toru Kawata (Syst. Comput. Jpn., 1986)

On area-efficient drawings of rectangular duals for VLSI floor-plan. - Katsunori Tani; Shuji Tsukiyama; Shoji Shinoda; Isao Shirakawa (Math. Program., 1991)

A distributed routing system for multilayer SOG. - Takashi Shimamoto; Hidetaka Hane; Isao Shirakawa; Shuji Tsukiyama; Shoji Shinoda; Nobuyasu Yui; Nobuyuki Nishiguchi (EURO-DAC, 1992)

An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan. - Shuji Tsukiyama; Keiichi Koike; Isao Shirakawa (Algorithmic Aspects of VLSI Layout, 1993)

Optimal layout recycling based on graph theoretic linear programming approach. - Yuji Shigehiro; Takashi Nagata; Isao Shirakawa; Takashi Kambe (VLSI, 1993)

Multi-Threaded Processor for Image Generation. - Takayuki Sagishima; Kozo Kimura; Hiroaki Hirata; Tokuzo Kiyohara; Shigeo Asahara; Takao Onoye; Isao Shirakawa (ISCAS, 1994)

A New Approach of Fractional-Dimension Based Module Clustering for VLSI Layout. - Masahiko Toyonaga; Shih-Tsung Yang; Toshiro Akino; Isao Shirakawa (ISCAS, 1994)

A layout approach to Monolithic Microwave IC. - Akira Nagao; Chiyoshi Yoshioka; Takashi Kambe; Isao Shirakawa (ASP-DAC, 1995)

A design of high-performance multiplier for digital video transmission. - Keisuke Okada; Shun Morikawa; Isao Shirakawa; Sumitaka Takeuchi (ASP-DAC, 1995)

Synthesis and simulation of digital demodulator for infrared data communication. - Hiroshi Uno; Toru Chiba; Keiji Kumatani; Isao Shirakawa (ASP-DAC, 1995)

Optimal Scheduling for Conditional Recource Sharing. - Akihisa Yamada 001; Satoru Nakamura; Nagisa Ishiura; Isao Shirakawa; Takashi Kambe (ISCAS, 1995)

VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding. - Toshihiro Masaki; Yasuo Morimoto; Takao Onoye; Isao Shirakawa (IEEE Trans. Circuits Syst. Video Technol., 1995)

Automatic layout recycling based on layout description and linear programming. - Yuji Shigehiro; Takashi Nagata; Isao Shirakawa; Itthichai Arungsrisangchai; Hiromitsu Takahashi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

A high performance FIR filter dedicated to digital video transmission. - Shun Morikawa; Keisuke Okada; Sumitaka Takeuchi; Isao Shirakawa (ASP-DAC, 1997)

Low-power H.263 video CoDec dedicated to mobile computing. - Morgan Hirosuke Miki; Gen Fujita; Takao Onoye; Isao Shirakawa (ISLPED, 1997)

Low power architecture for high speed infrared wireless communication system. - Hiroshi Uno; Keiji Kumatani; Hiroyuki Okuhata; Isao Shirakawa; Toru Chiba (ISLPED, 1997)

An object code compression approach to embedded processors. - Yukihiro Yoshida; Bao-Yu Song; Hiroyuki Okuhata; Takao Onoye; Isao Shirakawa (ISLPED, 1997)

Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visual Communication. - Koji Miyanohana; Gen Fujita; Kazuhiro Yanagida; Takao Onoye; Isao Shirakawa (J. Circuits Syst. Comput., 1997)

A Low Power Receiver Architecture for 4 Mbps Infrared Wireless Communication. - Hiroyuki Okuhata; Hiroshi Uno; Keiji Kumatani; Isao Shirakawa; Toru Chiba (J. Circuits Syst. Comput., 1997)

ASK digital demodulation scheme for noise immune infrared data communication. - Hiroshi Uno; Keiji Kumatani; Hiroyuki Okuhata; Isao Shirakawa; Toru Chiba (Wirel. Networks, 1997)

Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing. - Takao Onoye; Gen Fujita; Hiroyuki Okuhata; Morgan Hirosuke Miki; Isao Shirakawa (ASP-DAC, 1998)

Implementation of H.324 audiovisual codec for mobile computing. - Gen Fujita; Hiroyuki Okuhata; Morgan Hirosuke Miki; Takao Onoye; Isao Shirakawa (CICC, 1998)

An adaptive quantization algorithm for MPEG-2 video coding. - Lijun Luo; Cairong Zou; Zhenya He; Isao Shirakawa (ICASSP, 1998)

A low-power DSP core architecture for low bitrate speech codec. - Hiroyuki Okuhata; Morgan Hirosuke Miki; Takao Onoye; Isao Shirakawa (ICASSP, 1998)

A layout approach to monolithic microwave IC. - Akira Nagao; Isao Shirakawa; Takashi Kambe (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

FeRAM Circuit Technology for System on a Chip. - Koji Asari; Yukio Mitsuyama; Takao Onoye; Isao Shirakawa; Hiroshige Hirano; Toshiyuki Honda; Tatsuo Otsuki; Takaaki Baba; Teresa H. Meng (Evolvable Hardware, 1999)

Hybrid media-processor core for natural and synthetic video decoding. - Hideyuki Fujishima; Yusuke Takemoto; T. Yoneda; Takao Onoye; Isao Shirakawa (ISCAS (4), 1999)

Recursive maximum likelihood decoder for high-speed satellite communication. - Morgan Hirosuke Miki; Daisuke Taki; Gen Fujita; Takao Onoye; Isao Shirakawa; Toru Fujiwara; Tadao Kasami (ISCAS (4), 1999)

A wireless data processing system constructed of SAW-devices and its applications to medical cares. - Kenji Matsumura; Gen Fujita; Toshihiro Masaki; Isao Shirakawa; Hiroshi Inada (NSIP, 1999)

An architecture of a matrix-vector multiplier dedicated to video decoding and three-dimensional computer graphics. - Hideyuki Fujishima; Yusuke Takemoto; Takao Onoye; Isao Shirakawa (IEEE Trans. Circuits Syst. Video Technol., 1999)

Layout generation of array cell for NMOS 4-phase dynamic logic (short paper). - Makoto Furuie; Bao-Yu Song; Yukihiro Yoshida; Takao Onoye; Isao Shirakawa (ASP-DAC, 2000)

VLSI implementation of a realtime wavelet video coder. - Roberto Yusi Omaki; Yu Dong; M. Horgan Miki; Makoto Furuie; Shohei Yamada; Daisuke Taki; Masaya Tarui; Gen Fujita; Takao Onoye; Isao Shirakawa (CICC, 2000)

VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder. - Yu Dong; Roberto Yusi Omaki; Takao Onoye; Isao Shirakawa (ICIP, 2000)

A dynamically reconfigurable hardware-based cipher chip. - Yukio Mitsuyama; Zaldy Andales; Takao Onoye; Isao Shirakawa (ASP-DAC, 2001)

Realtime wavelet video coder based on reduced memory accessing. - Roberto Yusi Omaki; Yu Dong; Morgan Hirosuke Miki; Makoto Furuie; Daisuke Taki; Masaya Tarui; Gen Fujita; Takao Onoye; Isao Shirakawa (ASP-DAC, 2001)

Two-dimensional array layout for NMOS 4-phase dynamic logic. - Makoto Furuie; Takao Onoye; Shuji Tsukiyama; Isao Shirakawa (ICECS, 2001)

DSP implementation of 3D sound localization algorithm for monaural sound source. - Noriaki Sakamoto; Wataru Kobayashi; Takao Onoye; Isao Shirakawa (ICECS, 2001)

Evaluation of processor code efficiency for embedded systems. - Morgan Hirosuke Miki; Mamoru Sakamoto; Shingo Miyamoto; Yoshinori Takeuchi; Toyohiko Yoshida; Isao Shirakawa (ICS, 2001)

High Performance Java Hardware Engine and Software Kernel for Embedded Systems. - Morgan Hirosuke Miki; Motoki Kimura; Takao Onoye; Isao Shirakawa (VLSI-SOC, 2001)

VLSI architecture of dynamically reconfigurable hardware-based cipher. - Yukio Mitsuyama; Zaldy Andales; Takao Onoye; Isao Shirakawa (ISCAS (4), 2001)

Spatiotemporal segmentation for compact video representation. - Jianping Fan 001; Jun Yu 002; Gen Fujita; Takao Onoye; Lide Wu; Isao Shirakawa (Signal Process. Image Commun., 2001)

Realtime face object extraction algorithm for video phone. - Kenji Hontani; Takaaki Imanaka; Gen Fujita; Takao Onoye; Isao Shirakawa (APCCAS (1), 2002)

Embedded implementation of acoustic field enhancement for stereo headphones. - Nobuyuki Iwanaga; Wataru Kobayashi; Kazuhiko Furuya; Mamoru Sakamoto; Takao Onoye; Isao Shirakawa (APCCAS (1), 2002)

Parasitic capacitance modeling for multilevel interconnects. - Sadahiro Tani; Yoshihiro Uchida; Makoto Furuie; Shuji Tsukiyama; BuYeol Lee; Shuji Nishi; Yasushi Kubota; Isao Shirakawa; Shigeki Imai (APCCAS (1), 2002)

Burst mode: a new acceleration mode for 128-bit block ciphers. - Yukio Mitsuyama; Zaldy Andales; Takao Onoye; Isao Shirakawa (CICC, 2002)

OCEAN: Object Communication Environment for Arbitrary Network. - Katsuya Nakagawa; Masaru Kawakita; Koji Sato; Mitsuru Minakuchi; Osamu Tsumori; Keitaro Hanada; Toru Chiba; Isao Shirakawa (ICDCS Workshops, 2002)

Error correction block based ARQ protocol for wireless digital video transmission. - Yoshihiro Ohtani; N. Kawahara; T. Tomaru; K. Maruyama; Takao Onoye; Isao Shirakawa; Toru Chiba (ISCAS (1), 2002)

VLSI architecture of digital matched filter and prime interleaver for W-CDMA. - Yoshihiro Uchida; Masanao Ise; Takao Onoye; Isao Shirakawa; Itthichai Arungsrisangchai (ISCAS (3), 2002)

Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process. - Toshiyuki Kaya; Isao Shirakawa; Ryusuke Miyamoto; Takao Onoye (MTDT, 2002)

Code Efficiency Evaluation for Embedded Processors. - Morgan Hirosuke Miki; Mamoru Sakamoto; Shingo Miyamoto; Yoshinori Takeuchi; Toyohiko Yoshida; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Performance Estimation at Architecture Level for Embedded Systems. - Hiroshi Mizuno; Hiroyuki Kobayashi; Takao Onoye; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Error Detection by Digital Watermarking for MPEG-4 Video Coding. - Hiroyuki Okada; Altan-Erdene Shiitev; Hak-Sop Song; Gen Fujita; Takao Onoye; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

An Embedded Zerotree Wavelet Video Coding Algorithm with Reduced Memory Bandwidth. - Roberto Yusi Omaki; Gen Fujita; Takao Onoye; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Real-time face object extraction for video phone. - Kenji Hontani; Takaaki Imanaka; Gen Fujita; Takao Onoye; Isao Shirakawa (ICIP (3), 2003)

Interactive interface of realtime 3D sound movement for embedded applications. - Shinya Komata; Ablonczy Pal; Noriaki Sakamoto; Wataru Kobayashi; Takao Onoye; Isao Shirakawa (ISCAS (2), 2003)

Implementation of Java Accelerator for High-Performance Embedded Systems. - Motoki Kimura; Morgan Hirosuke Miki; Takao Onoye; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Object Sharing Scheme for Heterogeneous Environment. - Katsuya Nakagawa; Masaru Kawakita; Koji Sato; Mitsuru Minakuchi; Takao Onoye; Toru Chiba; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays. - Sadahiro Tani; Yoshihiro Uchida; Makoto Furuie; Shuji Tsukiyama; BuYeol Lee; Shuji Nishi; Yasushi Kubota; Isao Shirakawa; Shigeki Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Single DSP Implementation of Realtime 3D Sound Synthesis Algorithm. - Noriaki Sakamoto; Wataru Kobayashi; Takao Onoye; Isao Shirakawa (J. Circuits Syst. Comput., 2003)

Embedded implementation of acoustic field enhancement for stereo sound sources. - Nobuyuki Iwanaga; Wataru Kobayashi; Kazuhiko Furuya; Takao Onoye; Isao Shirakawa (IEEE Trans. Consumer Electron., 2003)

SoC design of Ogg Vorbis decoder using embedded processor. - Atsushi Kosaka; Satoshi Yamaguchi; Hiroyuki Okuhata; Takao Onoye; Isao Shirakawa (Conf. Computing Frontiers, 2004)

C-based hardware design of IMDCT accelerator for Ogg Vorbis decoder. - Shinichi Maeta; Atsushi Kosaka; Akihisa Yamada 001; Takao Onoye; Toru Chiba; Isao Shirakawa (EUSIPCO, 2004)

A design scheme for sampling switch in active matrix LCD. - Shingo Takahashi; Akira Taji; Shuji Tsukiyama; Masanori Hashimoto; Isao Shirakawa (ECCTD, 2005)

Interconnect capacitance extraction for system LCD circuits. - Yoshihiro Uchida; Sadahiro Tani; Masanori Hashimoto; Shuji Tsukiyama; Isao Shirakawa (ACM Great Lakes Symposium on VLSI, 2005)

3D sound movement system for embedded applications. - Tomoya Matsumura; Nobuyuki Iwanaga; Takao Onoye; Wataru Kobayashi; Isao Shirakawa; Itthichai Arungsrisangchai (ISCAS (5), 2005)

Design of Ogg Vorbis Decoder System for Embedded Platform. - Atsushi Kosaka; Hiroyuki Okuhata; Takao Onoye; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems. - Yukio Mitsuyama; Motoki Kimura; Takao Onoye; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Embedded 3D sound movement system based on feature extraction of head-related transfer function. - Tomoya Matsumura; Nobuyuki Iwanaga; Wataru Kobayashi; Takao Onoye; Isao Shirakawa (IEEE Trans. Consumer Electron., 2005)

W-CDMA Channel Codec by Configurable Processors. - Masanao Ise; Yasuhiro Ogasahara; Takao Onoye; Isao Shirakawa (Intell. Autom. Soft Comput., 2006)

Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation. - Gen Fujita; Takaaki Imanaka; Hyunh Van Nhat; Takao Onoye; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays. - Shingo Takahashi; Shuji Tsukiyama; Masanori Hashimoto; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A low-complexity FEC assignment scheme for motion JPEG2000 over wireless network. - Zhaohui Guo; Yuuki Nishikawa; Roberto Yusi Omaki; Takao Onoye; Isao Shirakawa (IEEE Trans. Consumer Electron., 2006)

Transistor Sizing of LCD Driver Circuit for Technology Migration. - Masanori Hashimoto; Takahito Ijichi; Shingo Takahashi; Shuji Tsukiyama; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Area-Efficient Reconfigurable Architecture for Media Processing. - Yukio Mitsuyama; Kazuma Takahashi; Rintaro Imai; Masanori Hashimoto; Takao Onoye; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

An automatic layout method for timing pulse generator of small LCD driver. - Shohei Asakawa; Shuji Tsukiyama; Isao Shirakawa; Shuji Nishi; Tadashi Takeda; Tomoyuki Nagai; Yasushi Kubota (ECCTD, 2011)

Implementation of super-resolution scaler for Full HD and 4K video. - Hiroyuki Okuhata; Masanao Ise; Roberto Yusi Omaki; Isao Shirakawa (ICCE-Berlin, 2013)

Live demonstration: A battery smart sensor for smart grid. - Lei Lin; N. Kawarabayashi; Masahiro Fukui; Isao Shirakawa (APCCAS, 2014)

Implementation of dynamic-range enhancement and super-resolution algorithms for medical image processing. - Hiroyuki Okuhata; Rintaro Imai; Masanao Ise; Roberto Yusi Omaki; Hajime Nakamura; Shinsuke Hara; Isao Shirakawa (ICCE, 2014)

A real-time vital sensing system for persons during exercises. - Shinsuke Hara; Takunori Shimazaki; Hiroyuki Okuhata; Isao Shirakawa; Hiroyuki Yomo (ICCE-Berlin, 2016)