3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time. - Ishan G. Thakkar; Sudeep Pasricha (ICCD, 2014)

A novel 3D graphics DRAM architecture for high-performance and low-energy memory accesses. - Ishan G. Thakkar; Sudeep Pasricha (ICCD, 2015)

3-D WiRED: A Novel WIDE I/O DRAM With Energy-Efficient 3-D Bank Organization. - Ishan G. Thakkar; Sudeep Pasricha (IEEE Des. Test, 2015)

3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead. - Ishan G. Thakkar; Sudeep Pasricha (IEEE Trans. Multi Scale Comput. Syst., 2015)

Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling. - Ishan G. Thakkar; Sai Vineel Reddy Chittamuru; Sudeep Pasricha (CODES+ISSS, 2016)

PICO: mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs. - Sai Vineel Reddy Chittamuru; Ishan G. Thakkar; Sudeep Pasricha (DAC, 2016)

Process variation aware crosstalk mitigation for DWDM based photonic NoC architectures. - Sai Vineel Reddy Chittamuru; Ishan G. Thakkar; Sudeep Pasricha (ISQED, 2016)

Run-time laser power management in photonic NoCs with on-chip semiconductor optical amplifiers. - Ishan G. Thakkar; Sai Vineel Reddy Chittamuru; Sudeep Pasricha (NOCS, 2016)

A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects. - Ishan G. Thakkar; Sai Vineel Reddy Chittamuru; Sudeep Pasricha (SLIP, 2016)

Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures. - Ishan G. Thakkar; Sudeep Pasricha (VLSID, 2016)

Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling. - Ishan G. Thakkar; Sai Vineel Reddy Chittamuru; Sudeep Pasricha (NOCS, 2017)

Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing. - Sai Vineel Reddy Chittamuru; Ishan G. Thakkar; Sudeep Pasricha (SLIP, 2017)

DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency. - Ishan G. Thakkar; Sudeep Pasricha (VLSID, 2017)

SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures. - Sai Vineel Reddy Chittamuru; Ishan G. Thakkar; Varun Bhat; Sudeep Pasricha (DAC, 2018)

Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-Chip. - Sudeep Pasricha; Sai Vineel Reddy Chittamuru; Ishan G. Thakkar (ACM Great Lakes Symposium on VLSI, 2018)

Mitigating the Energy Impacts of VBTI Aging in Photonic Networks-on-Chip Architectures with Multilevel Signaling. - Ishan G. Thakkar; Sudeep Pasricha (IGSC, 2018)

Securing Photonic NoC Architectures from Hardware Trojans. - Sudeep Pasricha; Sai Vineel Reddy Chittamuru; Ishan G. Thakkar; Varun Bhat (NOCS, 2018)

DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance. - Ishan G. Thakkar; Sudeep Pasricha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip. - Sai Vineel Reddy Chittamuru; Ishan G. Thakkar; Sudeep Pasricha (IEEE Trans. Multi Scale Comput. Syst., 2018)

HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs. - Sai Vineel Reddy Chittamuru; Ishan G. Thakkar; Sudeep Pasricha (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Mitigating Write Disturbance in Phase Change Memory Architectures. - Chao-Hsuan Huang; Ishan G. Thakkar (CASES (work in progress), 2019)

Mitigating inter-channel crosstalk non-uniformity in microring filter arrays of photonic NoCs: work-in-progress. - Venkata Sai Praneeth Karempudi; Ishan G. Thakkar (CODES+ISSS, 2019)

A scalable stochastic number generator for phase change memory based in-memory stochastic processing: work-in-progress. - Supreeth Mysore Shivanandamurthy; Ishan G. Thakkar; Sayed Ahmad Salehi (CODES+ISSS, 2019)

Redesigning Photonic Interconnects with Silicon-on-Sapphire Device Platform for Ultra-Low-Energy On-Chip Communication. - Venkata Sai Praneeth Karempudi; Sairam Sri Vatsavai; Ishan G. Thakkar (ACM Great Lakes Symposium on VLSI, 2020)

LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip. - Febin Sunny; Asif Mirza; Ishan G. Thakkar; Sudeep Pasricha; Mahdi Nikdast (ACM Great Lakes Symposium on VLSI, 2020)

Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. - Chao-Hsuan Huang; Ishan G. Thakkar (ICCD, 2020)

PROTEUS: Rule-Based Self-Adaptation in Photonic NoCs for Loss-Aware Co-Management of Laser Power and Performance. - Sairam Sri Vatsavai; Venkata Sai Praneeth Karempudi; Ishan G. Thakkar (NOCS, 2020)

Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. - Chao-Hsuan Huang; Ishan G. Thakkar (CoRR, 2020)

Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs. - Bobby Bose; Ishan G. Thakkar (ACM Great Lakes Symposium on VLSI, 2021)

ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing. - Supreeth Mysore Shivanandamurthy; Ishan G. Thakkar; Sayed Ahmad Salehi (ISVLSI, 2021)

Design Exploration and Scalability Analysis of a CMOS-Integrated, Polymorphic, Nanophotonic Arithmetic-Logic Unit. - Venkata Sai Praneeth Karempudi; Shreyan Datta; Ishan G. Thakkar (SenSys, 2021)

Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing. - Sairam Sri Vatsavai; Ishan G. Thakkar (VLSID, 2021)

ODIN: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-Situ Neural Network Processing in Phase Change RAM. - Supreeth Mysore Shivanandamurthy; Ishan G. Thakkar; Sayed Ahmad Salehi (CoRR, 2021)

Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks. - Sai Vineel Reddy Chittamuru; Ishan G. Thakkar; Sudeep Pasricha; Sairam Sri Vatsavai; Varun Bhat (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip. - Febin P. Sunny; Asif Mirza; Ishan G. Thakkar; Mahdi Nikdast; Sudeep Pasricha (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Silicon Nitride Microring Based High-Speed, Tuning-Efficient, Electro-Refractive Modulator. - Venkata Sai Praneeth Karempudi; Ishan G. Thakkar; Jeffrey Todd Hastings (iSES, 2022)

Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study. - Venkata Sai Praneeth Karempudi; Febin Sunny; Ishan G. Thakkar; Sai Vineel Reddy Chittamuru; Mahdi Nikdast; Sudeep Pasricha (ACM J. Emerg. Technol. Comput. Syst., 2022)

Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion. - Amlan Ganguly; Sergi Abadal; Ishan G. Thakkar; Natalie Enright Jerger; Marc D. Riedel; Masoud Babaie; Rajeev Balasubramonian; Abu Sebastian; Sudeep Pasricha; Baris Taskin (IEEE Micro, 2022)

Photonic Reconfigurable Accelerators for Efficient Inference of CNNs With Mixed-Sized Tensors. - Sairam Sri Vatsavai; Ishan G. Thakkar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures. - Ishan G. Thakkar; Sairam Sri Vatsavai; Venkata Sai Praneeth Karempudi (ACM Great Lakes Symposium on VLSI, 2023)

SCONNA: A Stochastic Computing Based Optical Accelerator for Ultra-Fast, Energy-Efficient Inference of Integer-Quantized CNNs. - Sairam Sri Vatsavai; Venkata Sai Praneeth Karempudi; Ishan G. Thakkar; Sayed Ahmad Salehi; Jeffrey Todd Hastings (IPDPS, 2023)

A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing Circuits. - Venkata Sai Praneeth Karempudi; Sairam Sri Vatsavai; Ishan G. Thakkar; Jeffrey Todd Hastings (ISQED, 2023)

AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning. - Supreeth Mysore Shivanandamurthy; Sairam Sri Vatsavai; Ishan G. Thakkar; Sayed Ahmad Salehi (ISQED, 2023)

An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural Networks. - Sairam Sri Vatsavai; Venkata Sai Praneeth Karempudi; Ishan G. Thakkar (ISQED, 2023)

A Bit-Parallel Deterministic Stochastic Multiplier. - Sairam Sri Vatsavai; Ishan G. Thakkar (ISQED, 2023)

A Silicon Nitride Microring Modulator for High-Performance Photonic Integrated Circuits. - Venkata Sai Praneeth Karempudi; Ishan G. Thakkar; Jeffrey Todd Hastings (CoRR, 2023)

Mixed Delay/Nondelay Embeddings Based Neuromorphic Computing with Patterned Nanomagnet Arrays. - Changpeng Ti; Usman Hassan; Sairam Sri Vatsavai; Margaret McCarter; Aastha Vasdev; Jincheng An; Barat Achinuq; Ulrich Welp; Sen-Ching S. Cheung; Ishan G. Thakkar; Jeffrey Todd Hastings (ICRC, 2024)

A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride Photonics. - Venkata Sai Praneeth Karempudi; Sairam Sri Vatsavai; Ishan G. Thakkar; Oluwaseun Adewunmi Alo; Jeffrey Todd Hastings; Justin Scott Woods (ISQED, 2024)

A Comparative Analysis of Microrings Based Incoherent Photonic GEMM Accelerators. - Sairam Sri Vatsavai; Venkata Sai Praneeth Karempudi; Oluwaseun Adewunmi Alo; Ishan G. Thakkar (ISQED, 2024)

Scaling Analog Photonic Accelerators for Byte-Size, Integer General Matrix Multiply (GEMM) Kernels. - Oluwaseun Adewunmi Alo; Sairam Sri Vatsavai; Ishan G. Thakkar (ISVLSI, 2024)

HEANA: A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference. - Sairam Sri Vatsavai; Venkata Sai Praneeth Karempudi; Ishan G. Thakkar (CoRR, 2024)

An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects. - Venkata Sai Praneeth Karempudi; Janibul Bashir; Ishan G. Thakkar (ACM J. Emerg. Technol. Comput. Syst., 2024)

ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks. - Salma Afifi; Ishan G. Thakkar; Sudeep Pasricha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

SafeLight: Enhancing Security in Optical Convolutional Neural Network Accelerators. - Salma Afifi; Ishan G. Thakkar; Sudeep Pasricha (DATE, 2025)

A Light-Speed Large Language Model Accelerator with Optical Stochastic Computing. - Salma Afifi; Oluwaseun Alo; Ishan G. Thakkar; Sudeep Pasricha (ACM Great Lakes Symposium on VLSI, 2025)

STAR: A Mixed Analog Stochastic In-DRAM Convolutional Neural Network Accelerator. - Salma Afifi; Ishan G. Thakkar; Sudeep Pasricha (IEEE Des. Test, 2025)

HEANA: A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference. - Sairam Sri Vatsavai; Venkata Sai Praneeth Karempudi; Ishan G. Thakkar (ACM Trans. Design Autom. Electr. Syst., 2025)