Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. - Ishwar Parulkar; Melvin A. Breuer; Charles Njinda (DAC, 1994)

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (DAC, 1995)

Lower Bounds on Test Resources for Scheduled Data Flow Graphs. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (DAC, 1996)

Introducing Redundant Computations in a Behavior for Reducing BIST Resources. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (DAC, 1998)

Scheduling and Module Assignment for Reducing Bist Resources. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (DATE, 1998)

Allocation Techniques for Reducing BIST Area Overhead of Data Paths. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (J. Electron. Test., 1998)

Estimation of BIST Resources During High-Level Synthesis. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (J. Electron. Test., 1998)

Introducing redundant computations in RTL data paths for reducing BIST resources. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (ACM Trans. Design Autom. Electr. Syst., 2001)

A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors. - Ishwar Parulkar; Thomas A. Ziaja; Rajesh Pendurkar; Anand D'Souza; Amitava Majumdar 002 (ITC, 2002)

Latch Divergency In Microprocessor Failure Analysis. - Peter Dahlgren; Paul Dickinson; Ishwar Parulkar (ITC, 2003)

Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems. - Ishwar Parulkar; Robert Cypher (IOLTS, 2005)

Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field. - Ishwar Parulkar; Dawei Huang; Leandro Chua Jr.; Drew Doblar (ITC, 2005)

Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems. - Iain Robertson; Graham Hetherington; Tom Leslie; Ishwar Parulkar; Ronald Lesnikoski (ITC, 2005)

Silent Data Corruption - Myth or reality? - Cristian Constantinescu; Ishwar Parulkar; R. Harper; Sarah Michalak (DSN, 2008)

Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® Processor. - Georgios K. Konstadinidis; Mamun Rashid; Peter F. Lai; Yukio Otaguro; Yannis Orginos; Sudhendra Parampalli; Mark Steigerwald; Shriram Gundala; Rambabu Pyapali; Leonard Rarick; Ilyas Elkin; Yuefei Ge; et al. (ISSCC, 2008)

DFX of a 3rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor. - Ishwar Parulkar; Sriram Anandakumar; Gaurav Agarwal; Gordon Liu; Krishna Rajan; Frank Chiu; Rajesh Pendurkar (ITC, 2008)

Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors. - Andreas Apostolakis; Mihalis Psarakis; Dimitris Gizopoulos; Antonis M. Paschalis; Ishwar Parulkar (ETS, 2009)

Comprehensive Approach to High-Performance Server Chipset Debug. - Ishwar Parulkar; Babu Turumella (IEEE Des. Test Comput., 2009)

Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor. - Georgios K. Konstadinidis; Marc Tremblay; Shailender Chaudhry; Mamun Rashid; Peter F. Lai; Yukio Otaguro; Yannis Orginos; Sudhendra Parampalli; Mark Steigerwald; Shriram Gundala; Rambabu Pyapali; Leonard Rarick; et al. (IEEE J. Solid State Circuits, 2009)

Panel: Reliability of data centers: Hardware vs. software. - Mehdi Baradaran Tahoori; Ishwar Parulkar; Dan Alexandrescu; Kevin Granlund; Allan Silburt; Bapi Vinnakota (DATE, 2010)