A restricted dynamically reconfigurable architecture for low power processors. - Takeshi Hirao; Dahoo Kim; Itaru Hida; Tetsuya Asai; Masato Motomura (ReConFig, 2013)

A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator. - Itaru Hida; Dahoo Kim; Tetsuya Asai; Masato Motomura (A-SSCC, 2014)

A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors. - Itaru Hida; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (APCCAS, 2016)