A 1 kbit Josephson random access memory using variable threshold cells. - Itaru Kurosawa; Hiroshi Nakagawa; Shin Kosaka; Masahiro Aoyagi; Susumu Takada (IEEE J. Solid State Circuits, 1989)

A Josephson 4 bit RALU for a prototype computer. - Hiroshi Nakagawa; Shin Kosaka; Hiroki Kawamura; Itaru Kurosawa; Masahiro Aoyagi; Youichi Hamazaki; Yoshikuni Okada; Susumu Takada (IEEE J. Solid State Circuits, 1989)

A Josephson 10-b instruction 128-word ROM unit. - Masahiro Aoyagi; Hiroshi Nakagawa; Itaru Kurosawa; Shin Kosaka; Yoshikuni Okada; Youichi Hamazaki; Susumu Takada (IEEE J. Solid State Circuits, 1990)

A fully operational 1 kb variable threshold Josephson RAM. - Itaru Kurosawa; Hiroshi Nakagawa; Masahiro Aoyagi; Shin Kosaka; Susumu Takada (IEEE J. Solid State Circuits, 1991)

Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits. - Masaaki Maezawa; Itaru Kurosawa; Yoshio Kameda; Takashi Nanya (ASYNC, 1996)

Special Section on Innovative Superconducting Devices and Their Applications. - Itaru Kurosawa (IEICE Trans. Electron., 2007)