General Results on Tour Lengths in Machines and Digraphs. - Takao Asano; Michiro Shibui; Itsuo Takanami (SIAM J. Comput., 1976)

A Note on Two-Dimensional Finite Automata. - Katsushi Inoue; Itsuo Takanami; Akira Nakamura (Inf. Process. Lett., 1978)

A note on closure properties of the classes of sets accepted by tape-bounded two-dimensional turing machines. - Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1978)

Cyclic closure properties of automata on a two-dimensional tape. - Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1978)

A Note on Cyclic Closure Operations. - Katsushi Inoue; Itsuo Takanami (Inf. Process. Lett., 1979)

A Note on Bottom-Up Pyramid Acceptors. - Katsushi Inoue; Itsuo Takanami (Inf. Process. Lett., 1979)

Three-way two-dimensional multicounter automata. - Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1979)

Closure properties of three-way and four-way tape-bounded two-dimensional turing machines. - Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1979)

Three-way tape-bounded two-dimensional turing machines. - Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1979)

On-line n-bounded multicounter automata. - Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1979)

One-Way Simple Multihead Finite Automata. - Katsushi Inoue; Itsuo Takanami; Akira Nakamura; Tadashi Ae (Theor. Comput. Sci., 1979)

A Note on Decision Problems for Three-Way Two-Dimensional Finite Automata. - Katsushi Inoue; Itsuo Takanami (Inf. Process. Lett., 1980)

A note on deterministic three-way tape-bounded two-dimensional Turing machines. - Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1980)

Errata: Corrections to two papers. - Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1980)

Nonclosure property of nondeterministic two-dimensional finite automata under cyclic closure. - Katsushi Inoue; Itsuo Takanami; Akira Nakamura (Inf. Sci., 1980)

Two-dimensional automata with rotated inputs. - Katsushi Inoue; Itsuo Takanami; Hiroshi Taniguchi (Inf. Sci., 1980)

Two-Dimensional Alternating Turing Machines with Only Universal States - Akira Ito 001; Katsushi Inoue; Itsuo Takanami; Hiroshi Taniguchi (Inf. Control., 1982)

A Note on Alternating On-Line Turing Machines. - Katsushi Inoue; Itsuo Takanami; Hiroshi Taniguchi (Inf. Process. Lett., 1982)

A note on rebound automata. - Katsushi Inoue; Itsuo Takanami; Hiroshi Taniguchi (Inf. Sci., 1982)

A note on three-dimensional finite automata. - Hiroshi Taniguchi; Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1982)

Two-dimensional automata with rotated inputs (projection-type). - Katsushi Inoue; Itsuo Takanami; Hiroshi Taniguchi (Inf. Sci., 1983)

A Relationship between Two-Dimensional Finite Automata and Three-Way Tape-Bounded Two-Dimensional Turing Machines. - Katsushi Inoue; Itsuo Takanami; Hiroshi Taniguchi (Theor. Comput. Sci., 1983)

Two-Dimensional Alternating Turing Machines. - Katsushi Inoue; Itsuo Takanami; Hiroshi Taniguchi (Theor. Comput. Sci., 1983)

Two-Dimensional Pattern Matching by Two-Dimensional on-Line Tessellation Acceptors. - Manabu Toda; Katsushi Inoue; Itsuo Takanami (Theor. Comput. Sci., 1983)

Connected pictures are not recognizable by deterministic two-dimensional on-line tessellation acceptors. - Katsushi Inoue; Itsuo Takanami; Akira Nakamura (Comput. Vis. Graph. Image Process., 1984)

A space-hierarchy result on two-dimensional alternating Turing machines with only universal states. - Katsushi Inoue; Akira Ito 001; Itsuo Takanami; Hiroshi Taniguchi (Inf. Sci., 1985)

Alternating On-Line Turing Machines with Only Universal States and Small Space Bounds. - Katsushi Inoue; Itsuo Takanami; Roland Vollmar (Theor. Comput. Sci., 1985)

Alternating Simple Multihead Finite Automata. - Hiroshi Matsuno; Katsushi Inoue; Hiroshi Taniguchi; Itsuo Takanami (Theor. Comput. Sci., 1985)

Three-way two-dimensional finite automata with rotated inputs. - Katsushi Inoue; Itsuo Takanami; Roland Vollmar (Inf. Sci., 1986)

Relationships of accepting powers between cellular space with bounded number of state-changes and other automata. - Akira Ito 001; Katsushi Inoue; Itsuo Takanami; Hiroshi Taniguchi (Syst. Comput. Jpn., 1986)

Relationship between the accepting powers of (k, l)-neighborhood template δ-type one-dimensional bounded cellular acceptors and other types of two-dimensional automata. - Hiroshi Taniguchi; Katsushi Inoue; Itsuo Takanami; Shigeko Seki (Syst. Comput. Jpn., 1986)

Hierarchical properties of the κ -neighborhood template A-type 2-dimensional bounded cellular acceptor. - Hiroshi Taniguchi; Katsushi Inoue; Itsuo Takanami (Syst. Comput. Jpn., 1987)

One-dimensional bounded cellular acceptor with rotated inputs. - Hiroshi Taniguchi; Katsushi Inoue; Itsuo Takanami (Syst. Comput. Jpn., 1987)

Some Considerations About NPRIORITY(1) Without ROM. - Katsushi Inoue; Itsuo Takanami (Inf. Process. Lett., 1988)

A note on three-way two-dimensional alternating Turing machines. - Akira Ito 001; Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1988)

The Simulation of Two-Dimensional One-Marker Automata by Three-Way Turing Machines. - Akira Ito 001; Katsushi Inoue; Itsuo Takanami (Int. J. Pattern Recognit. Artif. Intell., 1989)

Lower Bounds for Language Recognition on Two-Dimensional Alternating Multihead Machines. - Juraj Hromkovic; Katsushi Inoue; Itsuo Takanami (J. Comput. Syst. Sci., 1989)

One-Dimensional Bounded Cellular Acceptor with Rotated Inputs. A Relationship between ∧ and ∨ Types. - Hiroshi Taniguchi; Katsushi Inoue; Itsuo Takanami (Syst. Comput. Jpn., 1989)

A Leaf-Size Hierarchy of Two-Dimensional Alternating Turing Machines. - Katsushi Inoue; Itsuo Takanami; Juraj Hromkovic (Theor. Comput. Sci., 1989)

Deterministic Two-Dimensional On-Line Tessellation Acceptors are Equivalent to Two-Way Two-Dimensional Alternating Finite Automata Through 180°-Rotation. - Akira Ito 001; Katsushi Inoue; Itsuo Takanami (Theor. Comput. Sci., 1989)

The Simulation of Two-Dimensional One-Marker Automata by Three-Way Turing Machines. - Akira Ito 001; Katsushi Inoue; Itsuo Takanami (Array Grammars, Patterns and Recognizers, 1989)

Complexity of Acceptance Problems for Two-Dimensional Automata. - Akira Ito 001; Katsushi Inoue; Itsuo Takanami (A Perspective in Theoretical Computer Science, 1989)

A note on time-bounded bottom-up pyramid cellular acceptors. - Katsushi Inoue; Itsuo Takanami; Akira Nakamura (Inf. Sci., 1990)

Alternating Turing Machines with Modified Accepting Structure. - Katsushi Inoue; Akira Ito 001; Itsuo Takanami (Int. J. Found. Comput. Sci., 1991)

A survey of two-dimensional automata theory. - Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1991)

A Note on Real-Time One-Way Alternating Multicounter Machines. - Katsushi Inoue; Akira Ito 001; Itsuo Takanami (Theor. Comput. Sci., 1991)

Constant Leaf-Size Hierarchy of Two-Dimensional Alternating Turing Machines. - Akira Ito 001; Katsushi Inoue; Itsuo Takanami (ICPIA, 1992)

On the Power of One-Way Synchronized Alternating Machines with Small Space. - Juraj Hromkovic; Katsushi Inoue; Branislav Rovan; Anna Slobodová; Itsuo Takanami; Klaus W. Wagner (Int. J. Found. Comput. Sci., 1992)

Two Topics Concerning Two-Dimensional Automata Operating in Parallel. - Katsushi Inoue; Itsuo Sakuramoto; Makoto Sakamoto; Itsuo Takanami (Int. J. Pattern Recognit. Artif. Intell., 1992)

A Relationship Between Nondeterministic Turing Machines and 1-Inkdot Turing Machines with Small Space. - Katsushi Inoue; Akira Ito 001; Itsuo Takanami (Inf. Process. Lett., 1992)

A Note on Multi-Inkdot Nondeterministic Turing Machines with Small Space. - Katsushi Inoue; Akira Ito 001; Itsuo Takanami; Tsunehiro Yoshinaga (Inf. Process. Lett., 1993)

A note on three-dimensional alternating Turing machines with space smaller than log m. - Makoto Sakamoto; Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1993)

Construction of fault-tolerant mesh-connected highly parallel computer and its performance analysis. - Itsuo Takanami; Katsushi Inoue; Takahiro Watanabe; Minoru Oka (Syst. Comput. Jpn., 1993)

A Characterization of Recognizable Picture Languages. - Katsushi Inoue; Itsuo Takanami (Int. J. Pattern Recognit. Artif. Intell., 1994)

Constant Leaf-Size Hierarchy of Two-Dimensional Alternating Turing Machines. - Akira Ito 001; Katsushi Inoue; Itsuo Takanami; Yasuyoshi Inagaki (Int. J. Pattern Recognit. Artif. Intell., 1994)

Simulation of Three-Dimensional One-Marker Automata by Five-Way Turing Machines. - Makoto Sakamoto; Akira Ito 001; Katsushi Inoue; Itsuo Takanami (Inf. Sci., 1994)

On 1-inkdot Alternating Turing Machines with Small Space. - Katsushi Inoue; Akira Ito 001; Itsuo Takanami (Theor. Comput. Sci., 1994)

Reconfigurable architectures for mesh-arrays with PE and link faults. - Itsuo Takanami; Tadayoshi Horita (DFT, 1995)

The Effect of Inkdots for Two-Dimensional Automata. - Akira Ito 001; Katsushi Inoue; Itsuo Takanami; Yue Wang 002 (Int. J. Pattern Recognit. Artif. Intell., 1995)

Cooperating Systems of Three-Way, Two-Dimensional Finite Automata. - Yue Wang 002; Katsushi Inoue; Itsuo Takanami (Int. J. Pattern Recognit. Artif. Intell., 1995)

Optimal Simulation of Two-Dimensional Alternating Finite Automata by Three-Way Nondeterministic Turing Machines. - Akira Ito 001; Katsushi Inoue; Itsuo Takanami; Yue Wang 002 (Theor. Comput. Sci., 1995)

Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults. - Tadayoshi Horita; Itsuo Takanami (DFT, 1996)

On fault injection approaches for fault tolerance of feedforward neural networks. - Takehiro Ito; Itsuo Takanami (Asian Test Symposium, 1997)

Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. - Itsuo Takanami; Tadayoshi Horita (DFT, 1997)

A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults. - Tadayoshi Horita; Itsuo Takanami (ISPAN, 1997)

A built-in self-reconfigurable scheme for 3D mesh arrays. - Itsuo Takanami; Tadayoshi Horita (ISPAN, 1997)

Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions. - Tadayoshi Horita; Itsuo Takanami (ISPAN, 1999)

Built-in Self-Reconfiguring Systems for Mesh-Connected Processor Arrays with Spares on Two Rows/Columns. - Itsuo Takanami (DFT, 2000)

A Fault-Value Injection Approach for Multiple-Weight-Fault Tolerance of MNNs. - Itsuo Takanami; Masaru Sato; Yun Ping Yang (IJCNN (3), 2000)

A System for Efficiently Self-Reconstructing E-1½-Track Switch Torus Arrays. - Tadayoshi Horita; Itsuo Takanami (ISPAN, 2000)

A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays. - Tadayoshi Horita; Itsuo Takanami (PDPTA, 2000)

Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions. - Tadayoshi Horita; Itsuo Takanami (IEEE Trans. Computers, 2000)

Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement. - Itsuo Takanami (DFT, 2001)

Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types. - Tadayoshi Horita; Itsuo Takanami (PRDC, 2001)

An Extreme Value Injection Approach with Reduced Learning Time to Make MLNs Multiple-Weight-Fault Tolerant. - Itsuo Takanami; Yasuhiro Oyama (PRDC, 2002)

Self-Reconfiguring of 1½-Track-Switch Mesh Arrays with Spares on One Row and One Column by Simple Built-in Circuit. - Itsuo Takanami (IEICE Trans. Inf. Syst., 2004)

A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network. - Tadayoshi Horita; Takurou Murata; Itsuo Takanami (DFT, 2006)

An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches. - Tadayoshi Horita; Yuuji Katou; Itsuo Takanami (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant. - Tadayoshi Horita; Itsuo Takanami; Masatoshi Mori (IEICE Trans. Inf. Syst., 2008)

An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation. - Tadayoshi Horita; Itsuo Takanami (PDPTA, 2009)

Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant. - Kazuhiro Nishimura; Tadayoshi Horita; Masato Otsu; Itsuo Takanami (PDPTA, 2009)

An FPGA-based fast classifier with high generalization property. - Tadayoshi Horita; Itsuo Takanami (SIGARCH Comput. Archit. News, 2010)

An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications. - Tadayoshi Horita; Itsuo Takanami (Trans. Comput. Sci., 2011)

A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement. - Itsuo Takanami; Tadayoshi Horita (PRDC, 2012)

An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron. - Tadayoshi Horita; Itsuo Takanami (Neurocomputing, 2013)

A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings. - Tadayoshi Horita; Itsuo Takanami; Masakazu Akiba; Mina Terauchi; Tsuneo Kanno (MCSoC, 2014)

Multilayer Perceptrons Which Are Tolerant to Multiple Faults and Learnings to Realize Them. - Tadayoshi Horita; Itsuo Takanami; Kazuhiro Nishimura (Trans. Comput. Sci., 2014)

An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version). - Tadayoshi Horita; Itsuo Takanami; Masakazu Akiba; Mina Terauchi; Tsuneo Kanno (Trans. Comput. Sci., 2015)

A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement. - Itsuo Takanami; Tadayoshi Horita; Masakazu Akiba; Mina Terauchi; Tsuneo Kanno (Trans. Comput. Sci., 2016)

A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays with Spares on Diagonal. - Itsuo Takanami; Masaru Fukushi (PRDC, 2017)

Degradable Restructuring of Mesh-Connected Processor Arrays with Spares on Orthogonal Sides. - Itsuo Takanami; Masaru Fukushi (PRDC, 2018)

Restructuring Mesh-Connected Processor Arrays with Spares on Four Sides by Orthogonal Side Rotation. - Itsuo Takanami; Masaru Fukushi (PRDC, 2018)

A Built-In Circuit for Self-reconfiguring Mesh-Connected Processor Arrays with Spares on Diagonal. - Itsuo Takanami; Masaru Fukushi (Trans. Comput. Sci., 2019)

Self-restructuring of Mesh-Connected Processor Arrays with Spares Assigned on Rotated Orthogonal Side. - Itsuo Takanami; Masaru Fukushi; Takahiro Watanabe (Trans. Comput. Sci., 2021)

Degradable Self-restructuring of Processor Arrays by Direct Spare Replacement. - Itsuo Takanami; Masaru Fukushi (Trans. Comput. Sci., 2022)

Self-restructuring in Fault Tolerant Architecture - Processor Arrays with Spares - Itsuo Takanami (Springer, 2025)