System-level assessment and area evaluation of Spin Wave logic circuits. - Odysseas Zografos; Praveen Raghavan; Luca Gaetano Amarù; Bart Soree; Rudy Lauwereins; Iuliana P. Radu; Diederik Verkest; Aaron Thean (NANOARCH, 2014)

Area and routing efficiency of SWD circuits compared to advanced CMOS. - Odysseas Zografos; Praveen Raghavan; Yasser Sherazi; Adrien Vaysset; Florin Ciubotaru; Bart Soree; Rudy Lauwereins; Iuliana P. Radu; Aaron Thean (ICICDT, 2015)

Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective. - Tarun Agarwal; Iuliana P. Radu; Praveen Raghavan; Gianluca Fiori; Aaron Thean; Marc M. Heyns; Wim Dehaene (ESSCIRC, 2016)

Non-volatile spin wave majority gate at the nanoscale. - Odysseas Zografos; Sourav Dutta; Mauricio Manfrini; Adrien Vaysset; Bart Sorée; Azad Naeemi; Praveen Raghavan; Rudy Lauwereins; Iuliana P. Radu (CoRR, 2016)

Material selection and device design guidelines for two-dimensional materials based TFETs. - Tarun Agarwal; Bart Soree; Iuliana P. Radu; Praveen Raghavan; Gianluca Fiori; Marc M. Heyns; Wim Dehaene (ESSDERC, 2017)

Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures. - Yashwanth Balaji; Quentin Smets; Cesar J. Lockhart de la Rosa; Anh Khoa Augustin Lu; Daniele Chiappe; Tarun Agarwal; Dennis Lin; Cedric Huyghebaert; Iuliana P. Radu; Dan Mocuta; Guido Groeseneken (ESSDERC, 2017)

WS2 transistors on 300 mm wafers with BEOL compatibility. - Tom Schram; Quentin Smets; Benjamin Groven; M. H. Heyne; E. Kunnen; A. Thiam; Katia Devriendt; Annelies Delabie; Dennis Lin; M. Lux; Daniele Chiappe; I. Asselberghs; et al. (ESSDERC, 2017)

Towards high-performance polarity-controllable FETs with 2D materials. - Giovanni V. Resta; Jorge Romero Gonzalez; Yashwanth Balaji; Tarun Agarwal; Dennis Lin; Francky Catthoor; Iuliana P. Radu; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (DATE, 2018)

Spin-based majority gates for logic applications. - Iuliana P. Radu (DRC, 2018)

Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors. - Giovanni V. Resta; Yashwanth Balaji; Dennis Lin; Iuliana P. Radu; Francky Catthoor; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DRC, 2018)

Tunnel FETs using Phosphorene/ReS2 heterostructures. - Yashwanth Balaji; Quentin Smets; Dennis Lin; I. Asselberghs; Iuliana P. Radu; Guido Groeseneken (DRC, 2019)

Reconfigurable nanoscale spin wave majority gate with frequency-division multiplexing. - Giacomo Talmelli; Thibaut Devolder; Nick Träger; Johannes Förster; Sebastian Wintz; Markus Weigand; Hermann Stoll; Marc M. Heyns; Gisela Schütz; Iuliana P. Radu; Joachim Gräfe; Florin Ciubotaru; et al. (CoRR, 2019)

Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures. - Alexander Grill; Erik Bury; Jakob Michl; Stanislav Tyaginov; Dimitri Linten; Tibor Grasser; Bertrand Parvais; Ben Kaczer; Michael Waltl; Iuliana P. Radu (IRPS, 2020)

Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures. - Jakob Michl; Alexander Grill; Dieter Claes; Gerhard Rzepa; Ben Kaczer; Dimitri Linten; Iuliana P. Radu; Tibor Grasser; Michael Waltl (IRPS, 2020)

Circuit models for the co-simulation of superconducting quantum computing systems. - Rohith Acharya; Fahd A. Mohiyaddin; Anton Potocnik; Kristiaan De Greve; Bogdan Govoreanu; Iuliana P. Radu; Georges G. E. Gielen; Francky Catthoor (DATE, 2021)

On MX2-based metal-oxide-semiconductor device capacitance-voltage characteristics and dual-gate operation. - Dennis Lin; Xiangyu Wu; Vivek Mootheri; Daire Cott; Benjamin Groven; Pierre Morin; Inge Asselberghs; Iuliana P. Radu (DRC, 2021)

Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry. - Benjamin Gys; Fahd A. Mohiyaddin; Rohith Acharya; Roy Li; Kristiaan De Greve; Georges G. E. Gielen; Bogdan Govoreanu; Iuliana P. Radu; Francky Catthoor (ESSDERC, 2021)

Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing. - Iuliana P. Radu; Roy Li; Anton Potocnik; Tsvetan Ivanov; Danny Wan; Stefan Kubicek; Nard I. Dumoulin Stuyck; Jeroen Verjauw; Julien Jussot; Yann Canvel; Clement Godfrin; Massimo Mongillo; et al. (VLSI Circuits, 2021)

Uniform Spin Qubit Devices with Tunable Coupling in an All-Silicon 300 mm Integrated Process. - Nard I. Dumoulin Stuyck; Roy Li; Clement Godfrin; Asser Elsayed; Stefan Kubicek; Julien Jussot; B. T. Chan; Fahd A. Mohiyaddin; Mohamed Shehata; George Simion; Yann Canvel; Ludovic Goux; et al. (VLSI Circuits, 2021)

Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements. - Rohith Acharya; Anton Potocnik; Steven Brebels; Alexander Grill; Jeroen Verjauw; Tsvetan Ivanov; Daniel Perez Lozano; Danny Wan; Fahd A. Mohiyaddin; Jacques Van Damme; A. M. Vadiraj; Massimo Mongillo; et al. (VLSI Technology and Circuits, 2022)

Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor. - Ming-Yang Li; Ching-Hao Hsu; Shin-Wei Shen; Ang-Sheng Chou; Yuxuan Cosmi Lin; Chih-Piao Chuu; Ning Yang; Sui-An Chou; Lin-Yun Huang; Chao-Ching Cheng; Wei-Yen Woon; Szuya Liao; et al. (VLSI Technology and Circuits, 2022)

Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS. - Sheng-Kai Su; Edward Chen; Terry Y. T. Hung; Meng-Zhan Li; Gregory Pitner; Chao-Ching Cheng; Han Wang; Jin Cai; H.-S. Philip Wong; Iuliana P. Radu (VLSI Technology and Circuits, 2022)

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. - A. Vandooren; N. Parihar; Jacopo Franco; Roger Loo; Hiroaki Arimura; R. Rodriguez; F. Sebaai; S. Iacovo; Kevin Vandersmissen; W. Li; G. Mannaert; D. Radisic; et al. (VLSI Technology and Circuits, 2022)

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. - W.-C. Lin; H.-P. Huang; Kuo-Hsing Kao; Meng-Hsueh Chiang; Darsen D. Lu; Wei-Chou Hsu; Yeong-Her Wang; William Cheng-Yu Ma; Hann-Huei Tsai; Y.-J. Lee; H.-L. Chiang; J.-F. Wang; et al. (ESSDERC, 2023)

How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology. - H.-L. Chiang; Richard A. Hadi; J.-F. Wang; Hung-Chi Han; J.-J. Wu; H.-H. Hsieh; J.-J. Horng; W.-S. Chou; B.-S. Lien; C.-H. Chang; Y.-C. Chen; Yeong-Her Wang; et al. (VLSI Technology and Circuits, 2023)

Comprehensive 300 mm process for Silicon spin qubits with modular integration. - A. Elsayed; Clement Godfrin; Nard I. Dumoulin Stuyck; M. M. K. Shehata; Stefan Kubicek; S. Massar; Yann Canvel; Julien Jussot; Andriy Hikavyy; Roger Loo; George Simion; Massimo Mongillo; et al. (VLSI Technology and Circuits, 2023)

Building high performance transistors on carbon nanotube channel. - Gregory Pitner; Nathaniel Safron; Tzu-Ang Chao; Shengman Li; Sheng-Kai Su; Gilad Zeevi; Qing Lin; Hsin-Yuan Chiu; Matthias Passlack; Zichen Zhang 019; D. Mahaveer Sathaiya; Aslan Wei; et al. (VLSI Technology and Circuits, 2023)

Scaled contact length with low contact resistance in monolayer 2D channel transistors. - Wen-Chia Wu; Terry Y. T. Hung; D. Mahaveer Sathaiya; Dongxu Fan; Goutham Arutchelvan; Chen-Feng Hsu; Sheng-Kai Su; Ang-Sheng Chou; Edward Chen; Weisheng Li; Zhihao Yu; Hao Qiu; et al. (VLSI Technology and Circuits, 2023)

High Performance Transistor of Aligned Carbon Nanotubes in a Nanosheet Structure. - Nathaniel Safron; Tzu-Ang Chao; Shengman Li; Shreyam Natani; San Lin Liew; Carlo Gilardi; Hsin-Yuan Chiu; Sheng-Kai Su; Andrew Bechdolt; Gilad Zeevi; Zichen Zhang 019; Matthias Passlack; et al. (VLSI Technology and Circuits, 2024)

On the Extreme Scaling of Transistors with Monolayer MOS2 Channel. - Wen-Chia Wu; Terry Y. T. Hung; D. Mahaveer Sathaiya; Edward Chen; Chen-Feng Hsu; Walker Yun; Hsiang-Chi Hu; Bo-Heng Liu; T. Y. Lee; Chi-Chung Kei; Wen-Hao Chang; Jin Cai; et al. (VLSI Technology and Circuits, 2024)