Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL. - Ivan Blunno; Luciano Lavagno (ASYNC, 2000)

Designing low electro magnetic emissions circuits through clock skew optimization. - Ivan Blunno; Francesco Gregoretti; Claudio Passerone; D. Peretto; Leonardo M. Reyneri (ICECS, 2002)

Automating the design of an asynchronous DLX microprocessor. - Manish Amde; Ivan Blunno; Christos P. Sotiriou (DAC, 2003)

Handshake Protocols for De-Synchronization. - Ivan Blunno; Jordi Cortadella; Alex Kondratyev; Luciano Lavagno; Kelvin Lwin; Christos P. Sotiriou (ASYNC, 2004)

An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits Design. - Ivan Blunno; Guy Alain Narboni; Claudio Passerone (DSD, 2004)

Designing an asynchronous microcontroller using Pipefitter. - Ivan Blunno; Luciano Lavagno (IEEE Trans. Very Large Scale Integr. Syst., 2004)