SAW-Less Analog Front-End Receivers for TDD and FDD. - Ivan Fabiano; Marco Sosio; Antonio Liscidini; Rinaldo Castello (IEEE J. Solid State Circuits, 2013)

A 1.7-2.1GHz +23dBm TX power compatible blocker tolerant FDD receiver with integrated duplexer in 28nm CMOS. - Matteo Ramella; Ivan Fabiano; Danilo Manstretta; Rinaldo Castello (A-SSCC, 2015)

A 2.4GHz low-power SAW-less receiver for SoC coexistence. - Matteo Ramella; Ivan Fabiano; Danilo Manstretta; Rinaldo Castello (A-SSCC, 2015)

A SAW-Less 2.4-GHz Receiver Front-End With 2.4-mA Battery Current for SoC Coexistence. - Matteo Ramella; Ivan Fabiano; Danilo Manstretta; Rinaldo Castello (IEEE J. Solid State Circuits, 2017)

A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET. - Matteo Pisati; Fernando De Bernardinis; Paolo Pascale; Claudio Nani; Marco Sosio; Enrico Pozzati; Nicola Ghittori; Federico Magni; Marco Garampazzi; Giacomino Bollati; Antonio Milani; Alberto Minuti; et al. (ISSCC, 2019)

A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process. - Fabio Giunco; Marco Sosio; Claudio Nani; Ivan Fabiano; Travis Lovitt; Victor Karam; D. Albano; C. Asero; Nicola Codega; Marco Garampazzi; Nicola Ghittori; D. Herbas; et al. (VLSI Technology and Circuits, 2024)

A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz. - Claudio Nani; Enrico Monaco; Nicola Ghittori; Alessandro Bosi; Domenico Albano; Claudio Asero; Nicola Codega; Alessio Di Pasquo; Ivan Fabiano; Marco Garampazzi; Fabio Giunco; Leonardo Daniel Herbas Burgos; et al. (VLSI Technology and Circuits, 2024)

A 212Gb/s PAM-4 Retimer with Integrated High-Swing Optical Driver and Chip-to-Module Long Reach Capability of 40dB in 5nm FinFET. - V. Gurumoorthy; A. Tan; Amrutha Iyer; A. Fan; A. Farhoodfar; B. Alnabulsi; Belal Helal; Cindra Abidin; C. Loi; D. Cartina; H. Lo; Ivan Fabiano; et al. (ISSCC, 2025)

An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process. - Fabio Giunco; Marco Sosio; Claudio Nani; Ivan Fabiano; Travis Lovitt; Victor Karam; Domenico Albano; Claudio Asero; Nicola Codega; Marco Garampazzi; Nicola Ghittori; Leonardo Daniel Herbas Burgos; et al. (IEEE J. Solid State Circuits, 2025)

A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz. - Claudio Nani; Enrico Monaco; Nicola Ghittori; Alessandro Bosi; Domenico Albano; Claudio Asero; Nicola Codega; Alessio Di Pasquo; Ivan Fabiano; Marco Garampazzi; Fabio Giunco; Leonardo Daniel Herbas Burgos; et al. (IEEE J. Solid State Circuits, 2025)