A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach. - Ivan Miro Panades; Alain Greiner; Abbas Sheibanyrad (Nano-Net, 2006)

Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. - Abbas Sheibanyrad; Ivan Miro Panades; Alain Greiner (DATE, 2007)

Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures. - Ivan Miro Panades; Alain Greiner (NOCS, 2007)

Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. - Ivan Miro Panades; Fabien Clermidy; Pascal Vivet; Alain Greiner (NOCS, 2008)

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. - Abbas Sheibanyrad; Alain Greiner; Ivan Miro Panades (IEEE Des. Test Comput., 2008)

A 477mW NoC-based digital baseband for MIMO 4G SDR. - Fabien Clermidy; Christian Bernard; Romain Lemaire; Jérôme Martin; Ivan Miro Panades; Yvain Thonnart; Pascal Vivet; Norbert Wehn (ISSCC, 2010)

Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures. - Carolina Albea; Diego Puschini; Pascal Vivet; Ivan Miro Panades; Edith Beigné; Suzanne Lesecq (J. Low Power Electron., 2011)

Adaptive Stackable 3D Cache Architecture for Manycores. - Eric Guthmuller; Ivan Miro Panades; Alain Greiner (ISVLSI, 2012)

3D integration for power-efficient computing. - Denis Dutoit; Eric Guthmuller; Ivan Miro Panades (DATE, 2013)

A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. - Edith Beigné; Ivan Miro-Panades; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Farhat Thabet; Benoît Tain; K. Benchehida; Sylvain Engels; Robin Wilson; et al. (ESSCIRC, 2013)

3D stacking for multi-core architectures: From WIDEIO to distributed caches. - Fabien Clermidy; Denis Dutoit; Eric Guthmuller; Ivan Miro Panades; Pascal Vivet (ISCAS, 2013)

Architectural exploration of a fine-grained 3D cache for high performance in a manycore context. - Eric Guthmuller; Ivan Miro Panades; Alain Greiner (VLSI-SoC, 2013)

Power management through DVFS and dynamic body biasing in FD-SOI circuits. - Yeter Akgul; Diego Puschini; Suzanne Lesecq; Edith Beigné; Ivan Miro Panades; Pascal Benoit; Lionel Torres (DAC, 2014)

Shadow-scan design with low latency overhead and in-situ slack-time monitoring. - Sébastien Sarrazin; Samuel Evain; Ivan Miro Panades; Alexandre Valentian; Suresh Pajaniradja; Lirida Alves de Barros Naviner; Valentin Gherman (ETS, 2014)

Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths. - Sébastien Sarrazin; Samuel Evain; Ivan Miro Panades; Lirida Alves de Barros Naviner; Valentin Gherman (IOLTS, 2014)

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. - Robin Wilson; Edith Beigné; Philippe Flatresse; Alexandre Valentian; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; et al. (ISSCC, 2014)

A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. - Ivan Miro Panades; Edith Beigné; Yvain Thonnart; Laurent Alacoque; Pascal Vivet; Suzanne Lesecq; Diego Puschini; Anca Molnos; Farhat Thabet; Benoît Tain; Karim Ben Chehida; Sylvain Engels; et al. (IEEE J. Solid State Circuits, 2014)

3D advanced integration technology for heterogeneous systems. - Pascal Vivet; Christian Bernard; Fabien Clermidy; Denis Dutoit; Eric Guthmuller; Ivan Miro Panades; Gaël Pillonnet; Yvain Thonnart; Arnaud Garnier; Didier Lattard; Amandine Jouve; Franck Bana; et al. (3DIC, 2015)

Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. - Edith Beigné; Fabien Clermidy; Didier Lattard; Ivan Miro Panades; Yvain Thonnart; Pascal Vivet (ISCAS, 2015)

Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects. - Pascal Vivet; Christian Bernard; Eric Guthmuller; Ivan Miro Panades; Yvain Thonnart; Fabien Clermidy (ISVLSI, 2015)

An optical clock receiver based on an injection locked ring oscillator featuring auto-calibration. - Robert Polster; Jose-Luis Gonzalez Jimenez; Ivan Miro Panades; Eric Cassan (MWSCAS, 2015)

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. - Edith Beigné; Alexandre Valentian; Ivan Miro Panades; Robin Wilson; Philippe Flatresse; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; et al. (IEEE J. Solid State Circuits, 2015)

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Fady Abouzeid; et al. (COOL Chips, 2016)

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Cristiano Santos; Fabien Clermidy; Séverine Cheramy; Frédéric Pétrot; et al. (ISSCC, 2016)

In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. - Ivan Miro Panades; Edith Beigné; Olivier Billoint; Yvain Thonnart (IOLTS, 2017)

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Cristiano Santos; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Denis Dutoit; Fabien Clermidy; Séverine Cheramy; et al. (IEEE J. Solid State Circuits, 2017)

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Philippe Flatresse; et al. (IEEE Micro, 2017)

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. - Anuj Grover; G. S. Visweswaran; Chittoor R. Parthasarathy; Mohammad Daud; David Turgis; Bastien Giraud; Jean-Philippe Noel; Ivan Miro Panades; Guillaume Moritz; Edith Beigné; Philippe Flatresse; Promod Kumar; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. - Eric Guthmuller; César Fuguet Tortolero; Pascal Vivet; Christian Bernard; Ivan Miro Panades; Jean Durupt; E. Beignc; Didier Lattard; Séverine Cheramy; Alain Greiner; Quentin L. Meunier; Pirouz Bazargan-Sabet (ESSCIRC, 2018)

LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition. - Anthony Quelen; Guilherme Migliato Marega; Sylvain Bouquet; Ivan Miro Panades; Gaël Pillonnet (ESSCIRC, 2018)

Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols. - Mickael Maman; Dominique Morche; Baudouin Martineau; Clement Jany; Ivan Miro Panades; Anthony Quelen; Franck Badets; Edith Beigné (ICECS, 2018)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency. - Ivan Miro Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Anthony Quelen; Emmanuel Pluchart; Jean-Philippe Noel; Reda Boumchedda; et al. (VLSI Circuits, 2020)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)

Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems. - Davide Pala; Ivan Miro-Panades; Olivier Sentieys (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration. - Ivan Miro-Panades; Benoît Tain; Jean-Frédéric Christmann; David Coriat; Romain Lemaire; Clement Jany; Baudouin Martineau; Fabrice Chaix; Guillaume Waltener; Emmanuel Pluchart; Jean-Philippe Noel; Adam Makosiej; et al. (IEEE J. Solid State Circuits, 2023)

A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPS. - Ivan Miro-Panades; Vincent Lorrain; Lilian Billod; Inna Kucher; Vincent Templier; Sylvain Choisnet; Nermine Ali; Baptiste Rossigneux; Olivier Bichler; Alexandre Valentian (APCCAS, 2024)

Live Demonstration: A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPS. - Ivan Miro-Panades; Vincent Lorrain; Lilian Billod; Inna Kucher; Vincent Templier; Sylvain Choisnet; Nermine Ali; Baptiste Rossigneux; Olivier Bichler; Alexandre Valentian (APCCAS, 2024)

Low-Power Feature Extraction for BCI Applications Using Approximate Continuous Wavelet Transform. - Joe Saad; Adrian Evans; Ivan Miro-Panades; Tetiana Aksenova; Lorena Anghel (BCI, 2025)

Enabling a Portable Brain Computer Interface for Rehabilitation of Spinal Cord Injuries. - Adrian Evans; Victor Roux-Sibillon; Joe Saad; Ivan Miro-Panades; Tetiana Aksenova; Lorena Anghel (DATE, 2025)