Efficient Router Bypass via Hybrid Flow Control. - Ivan Perez 004; Enrique Vallejo 001; Ramón Beivide (NoCArc@MICRO, 2018)

Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip. - Neiel I. Leyva-Santes; Ivan Perez 004; César-Alejandro Hernández-Calderón; Enrique Vallejo 001; Miquel Moretó; Ramón Beivide; Marco Antonio Ramírez Salinas; Luis A. Villa-Vargas (ISUM, 2019)

SMART++: reducing cost and improving efficiency of multi-hop bypass in NoC routers. - Ivan Perez 004; Enrique Vallejo 001; Ramón Beivide (NOCS, 2019)

BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass. - Ivan Perez 004; Enrique Vallejo 001; Miquel Moretó; Ramón Beivide (ISPASS, 2020)

Efficient bypass in mesh and torus NoCs. - Ivan Perez 004; Enrique Vallejo 001; Ramón Beivide (J. Syst. Archit., 2020)

Information Reliability in Estimate Process: A Novel Blockchain Model. - Inés Borunda; Iván Pérez 004; Erwin Martínez; Alberto Ochoa-Zezzatti (Res. Comput. Sci., 2020)

PIugSMART: a pluggable open-source module to implement multihop bypass in networks-on-chip. - Alireza Monemi; Iván Pérez 004; Neiel Leyva; Enrique Vallejo 001; Ramón Beivide; Miquel Moretó (NOCS, 2021)

S-SMART++: A Low-Latency NoC Leveraging Speculative Bypass Requests. - Ivan Perez 004; Enrique Vallejo 001; Ramón Beivide (IEEE Trans. Computers, 2021)