The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4 GHz band. - Ivan Siu-Chuang Lu; Neil Weste; Sri Parameswaran (WCNC, 2005)

ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. - Ivan Siu-Chuang Lu; Neil Weste; Sri Parameswaran (VLSI Design, 2006)

A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider. - Ivan Siu-Chuang Lu; Neil Weste; Sri Parameswaran (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC. - Ivan Siu-Chuang Lu; Chi-Yao Yu; Yen-Horng Chen; Lan-chou Cho; Chih-hao Eric Sun; Chih-Chun Tang; George Chien (ISSCC, 2011)

A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC. - Chi-Yao Yu; Ivan Siu-Chuang Lu; Yen-Horng Chen; Lan-chou Cho; Chih-hao Eric Sun; Chih-Chun Tang; Hsiang-Hui Chang; Wen-Chang Lee; Sheng-Jui Huang; Tzung-Han Wu; Chinq-Shiun Chiu; George Chien (IEEE J. Solid State Circuits, 2011)

13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS. - Venumadhav Bhagavatula; Dae Hyun Kwon; Jaehun Lee; Quang-Diep Bui; Jeong-Hyun Choi; Siuchuang-Ivan Lu; Sang Won Son (ISSCC, 2017)

A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction. - Wanghua Wu; Chih-Wei Yao; Kunal Godbole; Ronghua Ni; Pei-Yuan Chiang; Yongping Han; Yongrong Zuo; Ashutosh Verma; Ivan Siu-Chuang Lu; Sang Won Son; Thomas Byunghak Cho (IEEE J. Solid State Circuits, 2019)

A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. - Ashutosh Verma; Venumadhav Bhagavatula; Amitoj Singh; Wanghua Wu; Hariharan Nagarajan; Pak-Kim Lau; Xiaohua Yu; Omar Elsayed; Ajaypat Jain; Anirban Sarkar 002; Fan Zhang; Che-Chun Kuo; et al. (ISSCC, 2022)

A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control. - Venumadhav Bhagavatula; Fan Zhang; Che-Chun Kuo; Anirban Sarkar 002; Ashutosh Verma; Tienyu Chang; Xiaohua Yu; Daeyoung Yoon; Ivan Siu-Chuang Lu; Sang Won Son; Thomas Byunghak Cho (IEEE J. Solid State Circuits, 2022)