Functional Tests for Ring-Address SRAM-type FIFOs. - Ad J. van de Goor; Yervant Zorian; Ivo Schanstra (EDAC-ETC-EUROASIC, 1994)

An Effective BIST Scheme for Ring-Address Type FIFOs. - Yervant Zorian; Ad J. van de Goor; Ivo Schanstra (ITC, 1994)

Fault models and tests for Ring Address Type FIFOs. - Ad J. van de Goor; Ivo Schanstra; Yervant Zorian (VTS, 1994)

Functional test for shifting-type FIFOs. - Ad J. van de Goor; Ivo Schanstra; Yervant Zorian (ED&TC, 1995)

Towards a Uniform Notation for Memory Tests. - Ad J. van de Goor; Aad Offerman; Ivo Schanstra (ED&TC, 1996)

Semiconductor manufacturing process monitoring using built-in self-test for embedded memories. - Ivo Schanstra; Dharmajaya Lukita; Ad J. van de Goor; Kees Veelenturf; Paul J. van Wijnen (ITC, 1998)

Industrial evaluation of stress combinations for march tests applied to SRAMs. - Ad J. van de Goor; Ivo Schanstra (ITC, 1999)

Address and Data Scrambling: Causes and Impact on Memory Tests. - Ad J. van de Goor; Ivo Schanstra (DELTA, 2002)

Consequences of RAM Bitline Twisting for Test Coverage. - Ivo Schanstra; Ad J. van de Goor (DATE, 2003)

Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. - Zaid Al-Ars; Martin Herzog; Ivo Schanstra; Ad J. van de Goor (MTDT, 2004)