Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1. - Ulrich Ramacher; Wolfgang Raab; Joachim K. Anlauf; J. A. Ulrich Hachmann; Jörg Beichter; Nico Brüls; Matthias Wesseling; Elisabeth Sicheneder; Reinhard Männer; Joachim Gläß; Andreas Wurz (Int. J. Neural Syst., 1993)

SYNAPSE-1: a high-speed general purpose parallel neurocomputer system. - Ulrich Ramacher; Wolfgang Raab; J. A. Ulrich Hachmann; Jörg Beichter; Nico Brüls; Matthias Wesseling; Elisabeth Sicheneder; Joachim Gläß; Andreas Wurz; Reinhard Männer (IPPS, 1995)

Integration of Instruction Set Simulators into SystemC High Level Models. - Ilia Oussorov; Wolfgang Raab; J. A. Ulrich Hachmann; Alex Kravtsov (DSD, 2002)

A 100-GOPS Programmable Processor for Vehicle Vision Systems. - Wolfgang Raab; Nico Brüls; J. A. Ulrich Hachmann; Jens Harnisch; Ulrich Ramacher; Christian Sauer 001; Axel Techmer (IEEE Des. Test Comput., 2003)

100 GOPS vision processor for automotive applications. - Ulrich Ramacher; Nico Brüls; J. A. Ulrich Hachmann; Jens Harnisch; Wolfgang Raab; Axel Techmer (SIGARCH Comput. Archit. News, 2003)

Embedded vision platform for video surveillance systems. - Axel Techmer; Hans-Martin Blüthgen; Cyprian Grassmann; J. A. Ulrich Hachmann; Wolfgang Raab; Ulrich Ramacher (Electronic Imaging: Image and Video Communications and Processing, 2005)

Low power design of the X-GOLD® SDR 20 baseband processor. - Wolfgang Raab; Jörg Berthold; J. A. Ulrich Hachmann; Dominik Langen; Michael Schreiner; Holger Eisenreich; Jens-Uwe Schluessler; Georg Ellguth (DATE, 2010)

Architecture and implementation of a Software-Defined Radio baseband processor. - Ulrich Ramacher; Wolfgang Raab; J. A. Ulrich Hachmann; Dominik Langen; Jörg Berthold; R. Kramer; A. Schackow; Cyprian Grassmann; Mirko Sauermann; P. Szreder; F. Capar; G. Obradovic; et al. (ISCAS, 2011)