0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems. - E. Shen; J. B. Kuo (ISCAS (4), 2002)

Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications. - G. Y. Liu; N. C. Wang; J. B. Kuo (ISCAS (5), 2005)

Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology. - B. Chung; J. B. Kuo (ISCAS, 2006)

Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique. - B. Chung; J. B. Kuo (PATMOS, 2006)

Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application. - B. Chung; J. B. Kuo (Integr., 2008)