Model-based clock synchronization in networks with drifting clocks. - Michael D. Lemmon; J. Ganguly; L. Xia (PRDC, 2000)

Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics. - J. P. Bastos; Barry J. O'Sullivan; Yusuke Higashi; Adrian Vaisman Chasin; Jacopo Franco; Hiroaki Arimura; J. Ganguly; Elena Capogreco; Alessio Spessot; N. Horiguchi (IRPS, 2024)

DRAM-Peri FinFET - A Thermally-Stable High-Performance Advanced CMOS RMG Platform with Mo-Based pWFM for sub-10nm DRAM. - J. Ganguly; Hiroaki Arimura; Romain Ritzenthaler; H. Bana; J. W. Maes; J. G. Lai; S. Brus; W. Maqsood; R. Sarkar; B. Kannan; Elena Capogreco; V. Machkaoutsan; et al. (VLSI Technology and Circuits, 2024)

Impact of Gate Metal Work Function on 1/f Noise in RMG MOSFETs. - R. Asanovski; Hiroaki Arimura; J. Ganguly; Pierpaolo Palestri; Alexander Grill; Ben Kaczer; Naoto Horiguchi; Luca Selmi; Jacopo Franco (IRPS, 2025)

Gate Stack Development for Next Gen High Voltage Periphery DRAM Devices. - J. P. Bastos; Jacopo Franco; Barry J. O'Sullivan; Yusuke Higashi; Adrian Chasin; J. Ganguly; Hiroaki Arimura; Alessio Spessot; M.-S. Kim; N. Horiguchi (IRPS, 2025)