VLSI Implementation of a linear systolic array. - J. Greg Nash; C. Petrozolin (ICASSP, 1985)

A systolic/cellular computer architecture for linear algebraic operations. - J. Greg Nash (ICRA, 1985)

The Systolic/Cellular System for Signal Processing. - J. Greg Nash; K. Wojtek Przytula; Siegfried Hansen (Computer, 1987)

Modified Faddeeva Algorithm for Concurrent Execution of Linear Algebraic Operations. - J. Greg Nash; Siegfried Hansen (IEEE Trans. Computers, 1988)

The image understanding architecture. - Charles C. Weems; Steven P. Levitan; Allen R. Hanson; Edward M. Riseman; David B. Shu; J. Gregory Nash (Int. J. Comput. Vis., 1989)

Parallel implementation of synthetic aperture radar algorithms. - K. Wojtek Przytula; J. Greg Nash (J. VLSI Signal Process., 1989)

A multiple-level heterogeneous architecture for image understanding. - David B. Shu; J. Gregory Nash; Charles C. Weems (ASAP, 1990)

Straight-line detection on a gated-connection VLSI network. - David B. Shu; J. Gregory Nash; Mary Mehrnoosh Eshaghian; K. Kim (ICPR (2), 1990)

An overview of architecture research for image understanding at the University of Massachusetts. - Charles C. Weems; Deepak Rana; Allen R. Hanson; Edward M. Riseman; David B. Shu; J. Gregory Nash (ICPR (2), 1990)

Parallel Implementation of Image Understanding Tasks on Gated-Connection Networks. - David B. Shu; J. Greg Nash; K. Kim (IPPS, 1991)

Heterogeneous Algorithms for Image Understanding Architecture. - Mary Mehrnoosh Eshaghian; J. Greg Nash; Muhammad E. Shaaban; David B. Shu (Parallel Algorithms Appl., 1993)

Automatic Latency-Optimal Design of FPGA-Based Systolic Arrays. - J. Greg Nash (FCCM, 2002)

Systolic Architecture for Computing the Discrete Fourier Transform on FPGAs. - J. Greg Nash (FCCM, 2005)

A New Class of High Performance FFTs. - J. Greg Nash (ICASSP (2), 2007)

A High Performance Scalable FFT. - J. Greg Nash (WCNC, 2007)

High-throughput programmable systolic array FFT architecture and FPGA implementations. - J. Greg Nash (ICNC, 2014)