A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit. - James B. Kuo; K. W. Su; J. H. Lou (ISCAS, 1994)

A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable for VLSI using low-voltage BiCMOS technology. - James B. Kuo; K. W. Su; J. H. Lou; S. S. Chen; C. S. Chiang (IEEE J. Solid State Circuits, 1995)

A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. - James B. Kuo; K. W. Su; J. H. Lou (IEEE J. Solid State Circuits, 1995)

A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI. - J. H. Lou; James B. Kuo (IEEE J. Solid State Circuits, 1997)

1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder. - J. H. Lou; James B. Kuo (ICECS, 1998)