A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication - Rourab Paul; Sangeet Saha; J. K. M. Sadique Uz Zaman; Suman Das; Amlan Chakrabarti; Ranjan Ghosh (CoRR, 2012)

A Review Study of NIST Statistical Test Suite: Development of an indigenous Computer Package - J. K. M. Sadique Uz Zaman; Ranjan Ghosh (CoRR, 2012)

Multiplicative Polynomial Inverse Over GF(73): Crisis of EEA and Its Solution. - J. K. M. Sadique Uz Zaman; Ranjan Ghosh (ACSS (2), 2014)

Dynamic Ciphering-15 Based on Multiplicative Polynomial Inverses Over Galois Field GF(73). - J. K. M. Sadique Uz Zaman; Sankhanil Dey; Ranjan Ghosh (ACSS (1), 2015)