RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor. - Aneesh Raveendran; Sandra Jean; J. Mervin; Vivian Desalphine; A. David Selvakumar (VDAT, 2019)

Side Channel Leakage Assessment Strategy On Attack Resistant AES Architectures. - Shabbir Darbar; J. Mervin; David Selvakumar (VDAT, 2020)

A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture. - Aneesh Raveendran; Sandra Jean; J. Mervin; Vivian Desalphine; David Selvakumar (VLSID, 2020)

A Randomized Montgomery Powering Ladder Exponentiation for Side-Channel Attack Resilient RSA and Leakage Assessment. - Venkata Reddy Kolagatla; J. Mervin; Shabbir Darbar; David Selvakumar; Sankha Saha (VDAT, 2021)

Formal Verification and Analysis of a Pseudo Random Number Generator. - David Selvakumar; J. Mervin; Shashikala Gunderao Pattanshetty; Vivian Desalphine (VDAT, 2021)