CDL - A tool for concurrent hardware and software development. - J. Robert Heath; Bill D. Carroll; Terry T. Cwik (DAC, 1977)

The Complexity and Use of a Multistage Interconnection Network for Distributed Processing Systems. - J. Robert Heath; James Cline (RTSS, 1980)

How to Write a Universal Cross-Assembler. - J. Robert Heath; Shailesh Patel (IEEE Micro, 1981)

A distributed computer architecture for real-time, data driven applications. - J. Robert Heath; George Broomell; Andrew D. Hurt (ICDCS, 1982)

The Design of a Fault-Tolerant Computing Element for Distributed Data Processors. - Andrew D. Hurt; J. Robert Heath (ICDCS, 1982)

A Hardware Task Scheduling Mechanism for a Real-Time Multi-Microprocessor Architecture. - Andrew D. Hurt; J. Robert Heath (RTSS, 1982)

Classification Categories and Historical Development of Circuit Switching Topologies. - George Broomell; J. Robert Heath (ACM Comput. Surv., 1983)

An Integrated-Circuit Crossbar Switching System Design. - George Broomell; J. Robert Heath (ICDCS, 1984)

A note on "Realization of digital filters using input-scaled floating-point arithmetic". - J. Robert Heath (IEEE Trans. Acoust. Speech Signal Process., 1986)

A methodology for the control and custom VLSI implementation of large-scale Clos networks. - J. Robert Heath; Eric Allen Disch (ICCD, 1988)

A new conflict resolving switchbox router. - Tae Won Cho; Sam S. Pyo; J. Robert Heath (Great Lakes Symposium on VLSI, 1992)

PARALLEX: a parallel approach to switchbox routing. - Tae Won Cho; Sam S. Pyo; J. Robert Heath (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Development, Analysis, and Verification of a Parallel Hybrid Dataflow Computer Architectural Framework and Associated Load-Balancing Strategies and Algorithms via Parallel Simulation. - J. Robert Heath; Balasubramanian Sivanesa (Simul., 1997)

High speed storage area networks using a fibre channel arbitrated loop interconnect. - J. Robert Heath; Peter Yakutis (IEEE Netw., 2000)

Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture. - J. Robert Heath; Andrew Tan (IEEE International Workshop on Rapid System Prototyping, 2001)

ESP: a flexible, high-performance, PLD-based network service. - M. Muthulakshmi; J. Robert Heath; Kenneth L. Calvert; James Griffioen (ICC, 2004)

New systolic array processor architecture for simultaneous discrete convolution of an image plane with multiple filter coefficient sets. - Albert T. Wong; J. Robert Heath; Michael Lhamon (J. Electronic Imaging, 2007)

A Hand-Held Programmable-Logic-Device Based Temperature and Relative-Humidity Sensor, Processor and Display System Platform for Automation and Control of Industry Processes. - Phani Tangirala; J. Robert Heath; Arthur Radun; Terry Conners (IAS, 2008)

Development and Validation of a Load Balancing and Control Mechanism for a Reconfigurable Single-Chip Heterogenous and Hybrid Multiprocessor Architecture Platform. - J. Robert Heath; Sridhar Hegde; Kanchan Bhide (PDCCS, 2009)

A New Reconfigurable Network Node Processor Architecture for Distributed Implementation of Ephemeral State Processing. - J. Robert Heath; Nien Y. Lim; Kenneth L. Calvert; Jim Griffioen (PDCCS, 2009)

A new multichannel, coherent amplitude modulated, time-division multiplexed, software-defined radio receiver architecture, and field-programmable-gate-array technology implementation. - Veerendra Bhargav Alluri; J. Robert Heath; Michael Lhamon (IEEE Trans. Signal Process., 2010)

FPGA based parallel architecture implementation of Stacked Error Diffusion algorithm. - Rishvanth Kora Venugopal; J. Robert Heath; Daniel L. Lau (SASP, 2011)