The cache and memory subsystems of the IBM POWER8 processor. - William J. Starke; Jeffrey Stuecheli; David Daly; J. S. Dodson; Florian Auernhammer; Patricia Sagmeister; Guy L. Guthrie; Charles F. Marino; M. S. Siegel; Bart Blaner (IBM J. Res. Dev., 2015)

IBM POWER9 memory architectures for optimized systems. - William J. Starke; J. S. Dodson; Jeffrey Stuecheli; Eric Retter; Brad W. Michael; Stephen J. Powell; James A. Marcella (IBM J. Res. Dev., 2018)