Test Pattern Generation with Restrictors. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (ITC, 1993)

Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O. - J. Th. van der Linden; M. H. Konijnenburg; Ad J. van de Goor (ITC, 1994)

Test generation and three-state elements, buses, and bidirectionals. - J. Th. van der Linden; M. H. Konijnenburg; Ad J. van de Goor (VTS, 1994)

Compact test sets for industrial circuits. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (VTS, 1995)

Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors. - J. Th. van der Linden; M. H. Konijnenburg; Ad J. van de Goor (Asian Test Symposium, 1996)

Accelerated Compact Test Set Generation for Three-State Circuits. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (ITC, 1996)

Sequential Test Generation with Advanced Illegal State Search. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (ITC, 1997)

Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection. - J. Th. van der Linden; M. H. Konijnenburg; Ad J. van de Goor (Asian Test Symposium, 1998)

Illegal State Space Identification for Sequential Circuit Test Generation. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (DATE, 1999)

Testability of the Philips 80C51 micro-controller. - M. H. Konijnenburg; J. Th. van der Linden; Ad J. van de Goor (ITC, 1999)

Test point insertion for compact test sets. - M. J. Geuzebroek; J. Th. van der Linden; Ad J. van de Goor (ITC, 2000)

Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. - M. J. Geuzebroek; J. Th. van der Linden; Ad J. van de Goor (ITC, 2002)