Bipolar transistor epilayer design using the MAIDS mixed-level simulator. - Leo C. N. de Vreede; Henk C. de Graaff; Joost A. Willemen; Wibo D. van Noort; Rik Jos; Lawrence E. Larson; Jan W. Slotboom; Joseph L. Tauritz (IEEE J. Solid State Circuits, 1999)

Reduction of UHF power transistor distortion with a nonuniform collector doping profile. - Wibo D. van Noort; Leo C. N. de Vreede; H. F. F. Jos; Lis K. Nanver; Jan W. Slotboom (IEEE J. Solid State Circuits, 2001)

Extraction and modeling of self-heating and mutual thermal coupling impedance of bipolar transistors. - Nebojsa Nenadovic; Slobodan Mijalkovic; Lis K. Nanver; Lode K. J. Vandamme; Vincenzo d'Alessandro; Hugo Schellevis; Jan W. Slotboom (IEEE J. Solid State Circuits, 2004)

A case study of ESD failures at random levels: analysis, explanation and solution. - T. Wu; Theo Smedes; J. P. Lokker; S.-N. Mei; J. W. Slotboom (Microelectron. Reliab., 2004)

Electrothermal characterization of silicon-on-glass VDMOSFETs. - Nebojsa Nenadovic; V. Cuoco; S. J. C. H. Theeuwen; Lis K. Nanver; Hugo Schellevis; G. Spierings; H. F. F. Jos; J. W. Slotboom (Microelectron. Reliab., 2005)