The importance of including thermal effects in estimating the effectiveness of power reduction techniques. - Ja Chun Ku; Maged Ghoneima; Yehea I. Ismail (CICC, 2005)

Power density minimization for highly-associative caches in embedded processors. - Ja Chun Ku; Serkan Ozdemir; Gokhan Memik; Yehea I. Ismail (ACM Great Lakes Symposium on VLSI, 2006)

A self-adjusting clock tree architecture to cope with temperature variations. - Jieyi Long; Ja Chun Ku; Seda Ogrenci Memik; Yehea I. Ismail (ICCAD, 2007)

Attaining Thermal Integrity in Nanometer Chips. - Ja Chun Ku; Yehea I. Ismail (ISCAS, 2007)

A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay. - Ja Chun Ku; Yehea I. Ismail (ISCAS, 2007)

Variable latency caches for nanoscale processor. - Serkan Ozdemir; Arindam Mallik; Ja Chun Ku; Gokhan Memik; Yehea I. Ismail (SC, 2007)

On the Scaling of Temperature-Dependent Effects. - Ja Chun Ku; Yehea I. Ismail (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. - Ja Chun Ku; Yehea I. Ismail (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Thermal Management of On-Chip Caches Through Power Density Minimization. - Ja Chun Ku; Serkan Ozdemir; Gokhan Memik; Yehea I. Ismail (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. - Ja Chun Ku; Yehea I. Ismail (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation. - Jieyi Long; Ja Chun Ku; Seda Ogrenci Memik; Yehea I. Ismail (IEEE Trans. Very Large Scale Integr. Syst., 2010)