A 12.5-Gb/s near-GND transceiver for wire-line UHD video interfaces. - Seok Kim; Jung-Myung Kang; Xuefan Jin; Se-Ung Park; Ja-Hoon Jin; Kee-Won Kwon; Jung-Hoon Chun; Jung Ho Lee; Jun Young Park; Dae Young Lee (ISCAS, 2014)

A 17.5-Gb/s transceiver with a MaxEye-based autonomous adaptation. - Ja-Hoon Jin; Xuefan Jin; Sang-Hoon Kim; Ik-Hwan Kim; Jaehong Jung; Kiwon Kwon; Jung-Hoon Chun (ISCAS, 2017)

A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique. - Jahoon Jin; Jaekwon Kim; Hye-Ran Kim; Canxing Piao; Jaemin Choi; Dong-Seok Kang; C. Jung-Hoon (ESSCIRC, 2018)

A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector. - Ja-Hoon Jin; Xuefan Jin; Jaehong Jung; Kiwon Kwon; Jintae Kim; Jung-Hoon Chun (IEEE J. Solid State Circuits, 2018)

A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based Adaptation Technique. - Ja-Hoon Jin; Seok Kim; Xuefan Jin; Sang-Hoon Kim; Jung-Hoon Chun (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Jitter-Tolerant Referenceless Digital-CDR for Cellular Transceivers. - Jaekwon Kim; Youngjun Ko; Jahoon Jin; Jaehyuk Choi 001; Jung-Hoon Chun (A-SSCC, 2020)

A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications. - Seki Kim; Hyongmin Lee; Yongjin Lee; Dongha Lee 004; Byeongbae Lee; Jahoon Jin; Susie Kim; Miri Noh; Kwonwoo Kang; Sangho Kim; Takahiro Nomiyama; Ji-Seon Paek; et al. (VLSI Technology and Circuits, 2022)

A 16/32 Gb/s Dual-Mode NRZ/PAM4 Voltage-Mode Transmitter With 2-Tap FFE. - Sung-Ha Kim; Byungwook Cho; Jahoon Jin; Yong Ho Song; Jung-Hoon Chun (IEEE Access, 2022)

A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization. - Jahoon Jin; Soo-Min Lee; Kyunghwan Min; Sodam Ju; Jihoon Lim; Hyunsu Chae; Kwonwoo Kang; Yunji Hong; Yeongcheol Jeong; Sang-Ho Kim; Jongwoo Lee; Joonsuk Kim (ISSCC, 2023)

A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces. - Kyunghwan Min; Jahoon Jin; Soo-Min Lee; Sodam Ju; Jisu Yook; Jihoon Lee; Yunji Hong; Sungsik Park; Sang-Ho Kim; Jongwoo Lee; Hyungjong Ko (VLSI Technology and Circuits, 2024)

A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization. - Jahoon Jin; Soo-Min Lee; Kyunghwan Min; Sodam Ju; Jihoon Lim; Jisu Yook; Jihoon Lee; Hyunsu Chae; Kwonwoo Kang; Yunji Hong; Yeongcheol Jeong; Sungsik Park; et al. (IEEE J. Solid State Circuits, 2024)