Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. - Alfredo Benso; Paolo Prinetto; Maurizio Rebaudengo; Matteo Sonza Reorda; Jaan Raik; Raimund Ubar (DFT, 1997)

Sequential Circuit Test Generation Using Decision Diagram Models. - Jaan Raik; Raimund Ubar (DATE, 1999)

Cycle-based Simulation with Decision Diagrams. - Raimund Ubar; Jaan Raik; Adam Morawiec (DATE, 1999)

High-level path activation technique to speed up sequential circuit test generation. - Jaan Raik; Raimund Ubar (ETW, 1999)

Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. - Adam Morawiec; Raimund Ubar; Jaan Raik (DATE, 2000)

Hierarchical defect-oriented fault simulation for digital circuits. - Mykola Blyzniuk; T. Cibáková; Elena Gramatová; Wieslaw Kuzmicz; M. Lobur; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (ETW, 2000)

Back-tracing and event-driven techniques in high-level simulation with decision diagrams. - Raimund Ubar; Jaan Raik; Adam Morawiec (ISCAS, 2000)

Efficient Hierarchical Approach to Test Generation for Digital Systems. - Raimund Ubar; Jaan Raik (ISQED, 2000)

Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. - Jaan Raik; Raimund Ubar (J. Electron. Test., 2000)

Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. - Wieslaw Kuzmicz; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (ISQED, 2001)

Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. - Mykola Blyzniuk; Irena Kazymyra; Wieslaw Kuzmicz; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (Microelectron. Reliab., 2001)

Internet-Based Collaborative Test Generation with MOSCITO. - André Schneider; Karl-Heinz Diener; Eero Ivask; Jaan Raik; Raimund Ubar; P. Miklos; T. Cibáková; Elena Gramatová (DATE, 2002)

Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. - Raimund Ubar; Jaan Raik; Eero Ivask; Marina Brik (DELTA, 2002)

Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods. - Jaan Raik; Artur Jutman; Raimund Ubar (ICECS, 2002)

Hierarchical test generation for combinational circuits with real defects coverage. - T. Cibáková; Mária Fischerová; Elena Gramatová; Wieslaw Kuzmicz; Witold A. Pleskacz; Jaan Raik; Raimund Ubar (Microelectron. Reliab., 2002)

Testing Strategies for Networks on Chip. - Raimund Ubar; Jaan Raik (Networks on Chip, 2003)

Multiple-objective backtrace for solving test generation constraints. - Andrei Mekler; Jaan Raik (SoC, 2003)

Evaluating Fault Emulation on FPGA. - Peeter Ellervee; Jaan Raik; Valentin Tihhomirov; Kalle Tammemäe (FPL, 2004)

Web-Based Environment for Digital Electronics Test Tools. - Eero Ivask; Jaan Raik; Raimund Ubar; André Schneider (Virtual Enterprises and Collaborative Networks, 2004)

An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. - Artur Jutman; Jaan Raik; Raimund Ubar; V. Vislogubov (DSD, 2005)

Improved Fault Emulation for Synchronous Sequential Circuits. - Jaan Raik; Peeter Ellervee; Valentin Tihhomirov; Raimund Ubar (DSD, 2005)

Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. - Joachim Sudbrock; Jaan Raik; Raimund Ubar; Wieslaw Kuzmicz; Witold A. Pleskacz (DSD, 2005)

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. - Jaan Raik; Raimund Ubar; Sergei Devadze; Artur Jutman (EDCC, 2005)

DOT: new deterministic defect-oriented ATPG tool. - Jaan Raik; Raimund Ubar; Joachim Sudbrock; Wieslaw Kuzmicz; Witold A. Pleskacz (ETS, 2005)

A New Testability Calculation Method to Guide RTL Test Generation. - Jaan Raik; Tanel Nõmmeots; Raimund Ubar (J. Electron. Test., 2005)

An External Test Approach for Network-on-a-Chip Switches. - Jaan Raik; Vineeth Govind; Raimund Ubar (ATS, 2006)

High-Level Decision Diagram based Fault Models for Targeting FSMs. - Jaan Raik; Raimund Ubar; Taavi Viilukas (DSD, 2006)

Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs. - Sergei Devadze; Jaan Raik; Artur Jutman; Raimund Ubar (LATW, 2006)

Layout to Logic Defect Analysis for Hierarchical Test Generation. - Maksim Jenihhin; Jaan Raik; Raimund Ubar; Witold A. Pleskacz; Michal Rakowski (DDECS, 2007)

Hierarchical Identification of Untestable Faults in Sequential Circuits. - Jaan Raik; Raimund Ubar; Anna Krivenko; Margus Kruus (DSD, 2007)

Fault Diagnosis in Integrated Circuits with BIST. - Raimund Ubar; Sergei Kostin; Jaan Raik; Teet Evartson; Harri Lensen (DSD, 2007)

Test Configurations for Diagnosing Faulty Links in NoC Switches. - Jaan Raik; Raimund Ubar; Vineeth Govind (ETS, 2007)

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (ETS, 2007)

FPGA-based fault emulation of synchronous sequential circuits. - Peeter Ellervee; Jaan Raik; Kalle Tammemäe; Raimund Ubar (IET Comput. Digit. Tech., 2007)

Parallel fault backtracing for calculation of fault coverage. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (ASP-DAC, 2008)

Untestable Fault Identification in Sequential Circuits Using Model-Checking. - Jaan Raik; Hideo Fujiwara; Raimund Ubar; Anna Krivenko (ATS, 2008)

Web-Based Framework for Parallel Distributed Test. - Eero Ivask; Jaan Raik; Raimund Ubar (DDECS, 2008)

Code Coverage Analysis using High-Level Decision Diagrams. - Jaan Raik; Uljana Reinsalu; Raimund Ubar; Maksim Jenihhin; Peeter Ellervee (DDECS, 2008)

Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. - Raimund Ubar; Sergei Devadze; Maksim Jenihhin; Jaan Raik; Gert Jervan; Peeter Ellervee (DELTA, 2008)

Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. - Witold A. Pleskacz; Maksim Jenihhin; Jaan Raik; Michal Rakowski; Raimund Ubar; Wieslaw Kuzmicz (DSD, 2008)

Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Raimund Ubar (ETS, 2008)

Reseeding using compaction of pre-generated LFSR sub-sequences. - Artur Jutman; Igor Aleksejev; Jaan Raik; Raimund Ubar (ICECS, 2008)

Distributed Approach for Genetic Test Generation in the Field of Digital Electronics. - Eero Ivask; Jaan Raik; Raimund Ubar (IDC, 2008)

Mixed hierarchical-functional fault models for targeting sequential cores. - Jaan Raik; Raimund Ubar; Taavi Viilukas; Maksim Jenihhin (J. Syst. Archit., 2008)

Embedded fault diagnosis in digital systems with BIST. - Raimund Ubar; Sergei Kostin; Jaan Raik (Microprocess. Microsystems, 2008)

Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. - Raimund Ubar; Sergei Kostin; Jaan Raik (DSD, 2009)

Structurally synthesized multiple input BDDs for simulation of digital circuits. - Raimund Ubar; Dmitri Mironov; Jaan Raik; Artur Jutman (ICECS, 2009)

High-Level Decision Diagrams based coverage metrics for verification and test. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Uljana Reinsalu; Raimund Ubar (LATW, 2009)

Investigations of the diagnosibility of digital networks with BIST. - Raimund Ubar; Sergei Kostin; Jaan Raik (LATW, 2009)

Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems. - Raimund Ubar; Artur Jutman; Jaan Raik; Sergei Kostin; Heinz-Dietrich Wuttke (MSE, 2009)

PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. - Maksim Jenihhin; Jaan Raik; Anton Chepurov; Raimund Ubar (J. Electron. Test., 2009)

Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. - Jaan Raik; Vineeth Govind; Raimund Ubar (IET Comput. Digit. Tech., 2009)

Parallel X-fault simulation with critical path tracing technique. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DATE, 2010)

Constraint-based test pattern generation at the Register-Transfer Level. - Taavi Viilukas; Jaan Raik; Maksim Jenihhin; Raimund Ubar; Anna Krivenko (DDECS, 2010)

Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DELTA, 2010)

Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. - Dmitri Mironov; Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DSD, 2010)

An approach for PSL assertion coverage analysis with high-level decision diagrams. - Maksim Jenihhin; Jaan Raik; Raimund Ubar; Tatjana Shchenova (EWDTS, 2010)

Fault collapsing with linear complexity in digital circuits. - Raimund Ubar; Dmitri Mironov; Jaan Raik; Artur Jutman (ISCAS, 2010)

Structural fault collapsing by superposition of BDDs for test generation in digital circuits. - Raimund Ubar; Dmitri Mironov; Jaan Raik; Artur Jutman (ISQED, 2010)

Mutation analysis with high-level decision diagrams. - Hanno Hantson; Jaan Raik; Maksim Jenihhin; Anton Chepurov; Raimund Ubar; Giuseppe Di Guglielmo; Franco Fummi (LATW, 2010)

Evolutionary Approach to Test Generation for Functional BIST - Yuriy A. Skobtsov; D. E. Ivanov; V. Y. Skobtsov; Raimund Ubar; Jaan Raik (CoRR, 2010)

Probabilistic equivalence checking based on high-level decision diagrams. - Anton Karputkin; Raimund Ubar; Mati Tombak; Jaan Raik (DDECS, 2011)

Defect-oriented module-level fault diagnosis in digital circuits. - Sergei Kostin; Raimund Ubar; Jaan Raik (DDECS, 2011)

Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. - Uljana Reinsalu; Jaan Raik; Raimund Ubar; Peeter Ellervee (DFT, 2011)

Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. - Jaan Raik; Anna Rannaste; Maksim Jenihhin; Taavi Viilukas; Raimund Ubar; Hideo Fujiwara (ETS, 2011)

Automated test bench generation for high-level synthesis flow ABELITE. - Taavi Viilukas; Maksim Jenihhin; Jaan Raik; Raimund Ubar; Samary Baranov (EWDTS, 2011)

Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. - Anton Karputkin; Raimund Ubar; Mati Tombak; Jaan Raik (HLDVT, 2011)

Mutation analysis for SystemC designs at TLM. - Valerio Guarnieri; Nicola Bombieri; Graziano Pravadelli; Franco Fummi; Hanno Hantson; Jaan Raik; Maksim Jenihhin; Raimund Ubar (LATW, 2011)

Low-area boundary BIST architecture for mesh-like network-on-chip. - Jaan Raik; Vineeth Govind (DDECS, 2012)

Multiple stuck-at-fault detection theorem. - Raimund Ubar; Sergei Kostin; Jaan Raik (DDECS, 2012)

How to Prove that a Circuit is Fault-Free? - Raimund Ubar; Sergei Kostin; Jaan Raik (DSD, 2012)

FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems design. - Jaan Raik (ETS, 2012)

Combining dynamic slicing and mutation operators for ESL correction. - Urmas Repinski; Hanno Hantson; Maksim Jenihhin; Jaan Raik; Raimund Ubar; Giuseppe Di Guglielmo; Graziano Pravadelli; Franco Fummi (ETS, 2012)

FoREnSiC- An Automatic Debugging Environment for C Programs. - Roderick Bloem; Rolf Drechsler; Görschwin Fey; Alexander Finder; Georg Hofferek; Robert Könighofer; Jaan Raik; Urmas Repinski; André Sülflow (Haifa Verification Conference, 2012)

Automated correction of design errors by edge redirection on High-Level Decision Diagrams. - Anton Karputkin; Raimund Ubar; Mati Tombak; Jaan Raik (ISQED, 2012)

Ultra-low latency NoC testing via pseudo-random test pattern compaction. - Hervé Tatenguem; Alessandro Strano; Vineeth Govind; Jaan Raik; Davide Bertozzi (ISSoC, 2012)

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis. - Hanno Hantson; Urmas Repinski; Jaan Raik; Maksim Jenihhin; Raimund Ubar (LATW, 2012)

PSL assertion checkers synthesis with ASM based HLS tool ABELITE. - Maksim Jenihhin; Samary Baranov; Jaan Raik; Valentin Tihhomirov (LATW, 2012)

About robustness of test patterns regarding multiple faults. - Raimund Ubar; Sergei Kostin; Jaan Raik (LATW, 2012)

Localization of Bugs in Processor Designs Using zamiaCAD Framework. - Anton Tsepurov; Valentin Tihhomirov; Maksim Jenihhin; Jaan Raik; Gunter Bartsch; Jorge Hernán Meza Escobar; Heinz-Dietrich Wuttke (MTV, 2012)

A scalable model based RTL framework zamiaCAD for static analysis. - Anton Tsepurov; Gunter Bartsch; Rainer Dorsch; Maksim Jenihhin; Jaan Raik; Valentin Tihhomirov (VLSI-SoC, 2012)

On the Reuse of TLM Mutation Analysis at RTL. - Valerio Guarnieri; Giuseppe Di Guglielmo; Nicola Bombieri; Graziano Pravadelli; Franco Fummi; Hanno Hantson; Jaan Raik; Maksim Jenihhin; Raimund Ubar (J. Electron. Test., 2012)

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. - Taavi Viilukas; Anton Karputkin; Jaan Raik; Maksim Jenihhin; Raimund Ubar; Hideo Fujiwara (J. Electron. Test., 2012)

Extensible open-source framework for translating RTL VHDL IP cores to SystemC. - Syed Saif Abrar; Maksim Jenihhin; Jaan Raik (DDECS, 2013)

Identifying NBTI-Critical Paths in Nanoscale Logic. - Raimund Ubar; Fabian Vargas 001; Maksim Jenihhin; Jaan Raik; Sergei Kostin; Letícia Maria Bolzani Poehls (DSD, 2013)

Synthesis of multiple fault oriented test groups from single fault test sets. - Raimund Ubar; Sergei Kostin; Jaan Raik (DTIS, 2013)

Comparison of Model-Based Error Localization algorithms for C designs. - Urmas Repinski; Jaan Raik (EWDTS, 2013)

Performance analysis of cosimulating processor core in VHDL and SystemC. - Syed Saif Abrar; Maksim Jenihhin; Jaan Raik; Shyam Kiran A.; C. Babu (ICACCI, 2013)

Assessment of diagnostic test for automated bug localization. - Valentin Tihhomirov; Anton Tsepurov; Maksim Jenihhin; Jaan Raik; Raimund Ubar (LATW, 2013)

At-speed self-testing of high-performance pipe-lined processing architectures. - Maksim Gorev; Raimund Ubar; Peeter Ellervee; Sergei Devadze; Jaan Raik; Mart Min (NORCHIP, 2013)

Automated design error debug using high-level decision diagrams and mutation operators. - Jaan Raik; Urmas Repinski; Anton Chepurov; Hanno Hantson; Raimund Ubar; Maksim Jenihhin (Microprocess. Microsystems, 2013)

Critical Path Tracing Based Simulation of Transition Delay Faults. - Jaak Kousaar; Raimund Ubar; Sergei Devadze; Jaan Raik (DSD, 2014)

Logic simulation and fault collapsing with shared structurally synthesized bdds. - Dmitri Mironov; Raimund Ubar; Jaan Raik (ETS, 2014)

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. - Marco Gaudesi; Maksim Jenihhin; Jaan Raik; Ernesto Sánchez 001; Giovanni Squillero; Valentin Tihhomirov; Raimund Ubar (EvoApplications, 2014)

Advanced technical education in the age of cyber physical systems. - Heinrich Theodor Vierhaus; Mario Schölzel; Jaan Raik; Raimund Ubar (EWME, 2014)

Hierarchical identification of NBTI-critical gates in nanoscale logic. - Sergei Kostin; Jaan Raik; Raimund Ubar; Maksim Jenihhin; Fabian Vargas 001; Letícia Maria Bolzani Poehls; Thiago Santos Copetti (LATW, 2014)

Automated Design Error Localization in RTL Designs. - Maksim Jenihhin; Anton Tsepurov; Valentin Tihhomirov; Jaan Raik; Hanno Hantson; Raimund Ubar; Gunter Bartsch; Jorge Hernán Meza Escobar; Heinz-Dietrich Wuttke (IEEE Des. Test, 2014)

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores. - Syed Saif Abrar; Maksim Jenihhin; Jaan Raik (DDECS, 2015)

New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. - Artjom Jasnetski; Jaan Raik; Anton Tsertov; Raimund Ubar (DDECS, 2015)

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. - Sergei Kostin; Jaan Raik; Raimund Ubar; Maksim Jenihhin; Thiago Copetti; Fabian Vargas 001; Letícia Maria Bolzani Pöhls (DDECS, 2015)

A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers. - Pietro Saltarelli; Behrad Niazmand; Jaan Raik; Ranganathan Hariharan; Gert Jervan; Thomas Hollstein (DSD, 2015)

FSMD RTL design manipulation for clock interface abstraction. - Syed Saif Abrar; Maksim Jenihhin; Jaan Raik (ICACCI, 2015)

Immortalizing many-core systems early experiences of the horizon 2020 action IMMORTAL. - Jaan Raik (HPCS, 2015)

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. - N. Palermo; Valentin Tihhomirov; Thiago Santos Copetti; Maksim Jenihhin; Jaan Raik; Sergei Kostin; Marco Gaudesi; Giovanni Squillero; Matteo Sonza Reorda; Fabian Vargas 001; Letícia Maria Bolzani Pöhls (LATS, 2015)

A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers. - Pietro Saltarelli; Behrad Niazmand; Jaan Raik; Vineeth Govind; Thomas Hollstein; Gert Jervan; Ranganathan Hariharan (NOCS, 2015)

Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits. - Raimund Ubar; Lembit Jurimagi; Jaan Raik (NORCAS, 2015)

Automated minimization of concurrent online checkers for Network-on-Chips. - Pietro Saltarelli; Behrad Niazmand; Ranganathan Hariharan; Jaan Raik; Gert Jervan; Thomas Hollstein (ReCoSoC, 2015)

Scalable algorithm for structural fault collapsing in digital circuits. - Raimund Ubar; Lembit Jurimagi; Elmet Orasson; Jaan Raik (VLSI-SoC, 2015)

Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs. - Raimund Ubar; Lembit Jürimägi; Elmet Orasson; Jaan Raik (VLSI-SoC (Selected Papers), 2015)

Functional self-test of high-performance pipe-lined signal processing architectures. - Maksim Gorev; Raimund Ubar; Peeter Ellervee; Sergei Devadze; Jaan Raik; Mart Min (Microprocess. Microsystems, 2015)

Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. - Jaak Kousaar; Raimund Ubar; Sergei Devadze; Jaan Raik (Microprocess. Microsystems, 2015)

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. - Francesco Pellerey; Maksim Jenihhin; Giovanni Squillero; Jaan Raik; Matteo Sonza Reorda; Valentin Tihhomirov; Raimund Ubar (ATS, 2016)

A synthesis-agnostic behavioral fault model for high gate-level fault coverage. - Anton Karputkin; Jaan Raik (DATE, 2016)

Designing reliable cyber-physical systems overview associated to the special session at FDL'16. - Gadi Aleksandrowicz; Eli Arbel; Roderick Bloem; Timon D. ter Braak; Sergei Devadze; Görschwin Fey; Maksim Jenihhin; Artur Jutman; Hans G. Kerkhoff; Robert Könighofer; Jan Malburg; Shiri Moran; et al. (FDL, 2016)

Gate-level modelling of NBTI-induced delays under process variations. - Thiago Copetti; Guilherme Medeiros Machado; Leticia Bolzani Poehls; Fabian Vargas 001; Sergei Kostin; Maksim Jenihhin; Jaan Raik; Raimund Ubar (LATS, 2016)

Logic-based implementation of fault-tolerant routing in 3D network-on-chips. - Behrad Niazmand; Siavoosh Payandeh Azad; José Flich; Jaan Raik; Gert Jervan; Thomas Hollstein (NOCS, 2016)

A novel random approach to diagnostic test generation. - Emmanuel Ovie Osimiry; Raimund Ubar; Sergei Kostin; Jaan Raik (NORCAS, 2016)

SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints. - Siavoosh Payandeh Azad; Behrad Niazmand; Peeter Ellervee; Jaan Raik; Gert Jervan; Thomas Hollstein (ReCoSoC, 2016)

Foreword. - Jaan Raik; Ian O'Connor; Thomas Hollstein; Krishnendu Chakrabarty (VLSI-SoC, 2016)

Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems. - Siavoosh Payandeh Azad; Behrad Niazmand; Jaan Raik; Gert Jervan; Thomas Hollstein (CoRR, 2016)

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. - Maksim Jenihhin; Giovanni Squillero; Thiago Santos Copetti; Valentin Tihhomirov; Sergei Kostin; Marco Gaudesi; Fabian Vargas 001; Jaan Raik; Matteo Sonza Reorda; Leticia Bolzani Poehls; Raimund Ubar; Guilherme Cardoso Medeiros (J. Electron. Test., 2016)

Resting EEG functional connectivity and graph theoretical measures for discrimination of depression. - Laura Orgo; Maie Bachmann; Kaia Kalev; M. Jarvelaid; Jaan Raik; Hiie Hinrikus (BHI, 2017)

BASTION: Board and SoC test instrumentation for ageing and no failure found. - Artur Jutman; Christophe Lotz; Erik Larsson; Matteo Sonza Reorda; Maksim Jenihhin; Jaan Raik; Hans G. Kerkhoff; Rene Krenz-Baath; Piet Engelke (DATE, 2017)

From online fault detection to fault management in Network-on-Chips: A ground-up approach. - Siavoosh Payandeh Azad; Behrad Niazmand; Karl Janson; Nevin George; Stephen Adeboye Oyeniran; Tsotne Putkaradze; Apneet Kaur; Jaan Raik; Gert Jervan; Raimund Ubar; Thomas Hollstein (DDECS, 2017)

A scalable technique to identify true critical paths in sequential circuits. - Raimund Ubar; Sergei Kostin; Maksim Jenihhin; Jaan Raik (DDECS, 2017)

Automated area and coverage optimization of minimal latency checkers. - Siavoosh Payandeh Azad; Behrad Niazmand; Apneet Kaur Sandhu; Jaan Raik; Gert Jervan; Thomas Hollstein (ETS, 2017)

Multi-Fragment Markov Model Guided Online Test Generation for MPSoC. - Jüri Vain; Leonidas Tsiopoulos; Vyacheslav S. Kharchenko; Apneet Kaur; Maksim Jenihhin; Jaan Raik (ICTERI, 2017)

Comprehensive performance and robustness analysis of 2D turn models for network-on-chips. - Siavoosh Payandeh Azad; Behrad Niazmand; Karl Janson; Thilo Kogge; Jaan Raik; Gert Jervan; Thomas Hollstein (ISCAS, 2017)

High-level test generation for processing elements in many-core systems. - Stephen Adeboye Oyeniran; Raimund Ubar; Siavoosh Payandeh Azad; Jaan Raik (ReCoSoC, 2017)

Fault-resilient NoC router with transparent resource allocation. - Tsotne Putkaradze; Siavoosh Payandeh Azad; Behrad Niazmand; Jaan Raik; Gert Jervan (ReCoSoC, 2017)

Modeling and simulation of circuits with shared structurally synthesized BDDs. - Raimund Ubar; Lembit Jürimägi; Jaan Raik; Vladimir Viies (Microprocess. Microsystems, 2017)

From RTL Liveness Assertions to Cost-Effective Hardware Checkers. - Ranganathan Hariharan; Tara Ghasempouri; Behrad Niazmand; Jaan Raik (DCIS, 2018)

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications. - Serhiy Avramenko; Siavoosh Payandeh Azad; Stefano Esposito; Behrad Niazmand; Massimo Violante; Jaan Raik; Maksim Jenihhin (DDECS, 2018)

Software-Level TMR Approach for On-Board Data Processing in Space Applications. - Karl Janson; Carl Johann Treudler; Thomas Hollstein; Jaan Raik; Maksim Jenihhin; Görschwin Fey (DDECS, 2018)

Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling. - Robert Schmidt 003; Rehab Massoud; Jaan Raik; Alberto García Ortiz; Rolf Drechsler (IOLTS, 2018)

An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics. - Tara Ghasempouri; Siavoosh Payandeh Azad; Behrad Niazmand; Jaan Raik (ITC-Asia, 2018)

A Hierarchical Approach for Devising Area Efficient Concurrent Online Checkers. - Behrad Niazmand; Siavoosh Payandeh Azad; Tara Ghasempouri; Jaan Raik; Gert Jervan (ITC-Asia, 2018)

Timing-critical path analysis with structurally synthesized BDDs. - Raimund Ubar; Lembit Jurimagi; Maksim Jenihhin; Jaan Raik; Niyi-Leigh Olugbenga; Vladimir Viies (MECO, 2018)

Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. - Jaak Kousaar; Raimund Ubar; Sergei Kostin; Sergei Devadze; Jaan Raik (MIXDES, 2018)

Towards Multidimensional Verification: Where Functional Meets Non-Functional. - Maksim Jenihhin; Xinhui Lai; Tara Ghasempouri; Jaan Raik (NORCAS, 2018)

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. - Lembit Jurimagi; Raimund Ubar; Maksim Jenihhin; Jaan Raik; Sergei Devadze; Sergei Kostin (PATMOS, 2018)

AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links. - Karl Janson; Rene Pihlak; Siavoosh Payandeh Azad; Behrad Niazmand; Gert Jervan; Jaan Raik (ReCoSoC, 2018)

Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis. - Serhiy Avramenko; Siavoosh Payandeh Azad; Behrad Niazmand; Massimo Violante; Jaan Raik; Maksim Jenihhin (VLSI-SoC, 2018)

Design Understanding: From Logic to Specification*. - Görschwin Fey; Tara Ghasempouri; Swen Jacobs; Gianluca Martino; Jaan Raik; Heinz Riener (VLSI-SoC, 2018)

Fast identification of true critical paths in sequential circuits. - Raimund Ubar; Sergei Kostin; Maksim Jenihhin; Jaan Raik; Lembit Jürimägi (Microelectron. Reliab., 2018)

New categories of Safe Faults in a processor-based Embedded System. - Cemil Cem Gürsoy; Maksim Jenihhin; Adeboye Stephen Oyeniran; Davide Piumatti; Jaan Raik; Matteo Sonza Reorda; Raimund Ubar (DDECS, 2019)

Fault-Aware Performance Assessment Approach for Embedded Networks. - Jan Malburg; Karl Janson; Jaan Raik; Frank Dannemann (DDECS, 2019)

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (ETS, 2019)

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. - Saba Yousefzadeh; Katayoon Basharkhah; Nooshin Nosrati; Rezgar Sadeghi; Jaan Raik; Maksim Jenihhin; Zainalabedin Navabi (EWDTS, 2019)

RTL Assertion Mining with Automated RTL-to-TLM Abstraction. - Tara Ghasempouri; Alessandro Danese; Graziano Pravadelli; Nicola Bombieri; Jaan Raik (FDL, 2019)

Efficient Fault Injection based on Dynamic HDL Slicing Technique. - Ahmet Cagri Bagbaba; Maksim Jenihhin; Jaan Raik; Christian Sauer 001 (IOLTS, 2019)

Application Specific True Critical Paths Identification in Sequential Circuits. - Lembit Jürimägi; Raimund Ubar; Maksim Jenihhin; Jaan Raik; Sergei Devadze; Adeboye Stephen Oyeniran (IOLTS, 2019)

PASCAL: Timing SCA Resistant Design and Verification Flow. - Xinhui Lai; Maksim Jenihhin; Jaan Raik; Kolin Paul (IOLTS, 2019)

IEEE European Test Symposium (ETS). - Stephan Eggersglüß; Said Hamdioui; Artur Jutman; Maria K. Michael; Jaan Raik; Matteo Sonza Reorda; Mehdi Baradaran Tahoori; Elena-Ioana Vatajelu (ITC, 2019)

Software-Based Mitigation for Memory Address Decoder Aging. - Daniel H. P. Kraak; Cemil Cem Gürsoy; Innocent O. Agbo; Mottaqiallah Taouil; Maksim Jenihhin; Jaan Raik; Said Hamdioui (LATS, 2019)

Mixed-level identification of fault redundancy in microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (LATS, 2019)

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. - Ahmet Cagri Bagbaba; Maksim Jenihhin; Jaan Raik; Christian Sauer 001 (NORCAS, 2019)

Engineering of an Effective Automatic Dynamic Assertion Mining Platform. - Tara Ghasempouri; Jan Malburg; Alessandro Danese; Graziano Pravadelli; Görschwin Fey; Jaan Raik (VLSI-SoC, 2019)

Implementation-Independent Functional Test Generation for MSC Microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (VLSI-SoC, 2019)

On Test Generation for Microprocessors for Extended Class of Functional Faults. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (VLSI-SoC (Selected Papers), 2019)

High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Cemil Cem Gürsoy; Jaan Raik (CoRR, 2019)

Overview of Fault Tolerant Techniques in Underwater Sensor Networks. - Lauri Vihman; Maarja Kruusmaa; Jaan Raik (CoRR, 2019)

Understanding multidimensional verification: Where functional meets non-functional. - Xinhui Lai; Aneesh Balakrishnan; Thomas Lange; Maksim Jenihhin; Tara Ghasempouri; Jaan Raik; Dan Alexandrescu (Microprocess. Microsystems, 2019)

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. - Maksim Jenihhin; Said Hamdioui; Matteo Sonza Reorda; Milos Krstic; Peter Langendörfer; Christian Sauer 001; Anton Klotz; Michael Hübner 001; Jörg Nolte; Heinrich Theodor Vierhaus; Georgios N. Selimis; Dan Alexandrescu; et al. (DATE, 2020)

A Security Verification Template to Assess Cache Architecture Vulnerabilities. - Tara Ghasempouri; Jaan Raik; Kolin Paul; Cezar Reinbrecht; Said Hamdioui; Mottaqiallah Taouil (DDECS, 2020)

Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (DSD, 2020)

Adjustable self-healing methodology for accelerated functions in heterogeneous systems. - Mohammad Riazati; Tara Ghasempouri; Masoud Daneshtalab; Jaan Raik; Mikael Sjödin; Björn Lisper (DSD, 2020)

SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks. - Ameer Shalabi; Tara Ghasempouri; Peeter Ellervee; Jaan Raik (DSD, 2020)

Data-Driven Cross-Layer Fault Management Architecture for Sensor Networks. - Lauri Vihman; Maarja Kruusmaa; Jaan Raik (EDCC, 2020)

LiD-CAT: A Lightweight Detector for Cache ATtacks. - Cezar Reinbrecht; Said Hamdioui; Mottaqiallah Taouil; Behrad Niazmand; Tara Ghasempouri; Jaan Raik; Johanna Sepúlveda (ETS, 2020)

An Efficient FPGA-based Architecture for Contractive Autoencoders. - Madis Kerner; Kalle Tammemäe; Jaan Raik; Thomas Hollstein (FCCM, 2020)

NV-SP: A New High Performance and Low Energy NVM-Based Scratch Pad. - Ameer Shalabi; Kolin Paul; Tara Ghasempouri; Jaan Raik (ISVLSI, 2020)

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. - Adeboye Stephen Oyeniran; Raimund Ubar; Maksim Jenihhin; Jaan Raik (J. Electron. Test., 2020)

Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs. - Lembit Jürimägi; Raimund Ubar; Maksim Jenihhin; Jaan Raik (Microprocess. Microsystems, 2020)

Side-Channel Attacks on Triple Modular Redundancy Schemes. - Felipe Almeida; Levent Aksoy; Jaan Raik; Samuel Pagliarini (ATS, 2021)

Triple Fixed-Point MAC Unit for Deep Learning. - Madis Kerner; Kalle Tammemäe; Jaan Raik; Thomas Hollstein (DATE, 2021)

CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector. - Ameer Shalabi; Tara Ghasempouri; Peeter Ellervee; Jaan Raik (DDECS, 2021)

Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. - Maksim Jenihhin; Adeboye Stephen Oyeniran; Jaan Raik; Raimund Ubar (DSD, 2021)

High-level Intellectual Property Obfuscation via Decoy Constants. - Levent Aksoy; Quang-Linh Nguyen; Felipe Almeida; Jaan Raik; Marie-Lise Flottes; Sophie Dupuis; Samuel Pagliarini (IOLTS, 2021)

A Methodology for Automated Mining of Compact and Accurate Assertion Sets. - Mohammad Reza Heidari Iman; Jaan Raik; Maksim Jenihhin; Gert Jervan; Tara Ghasempouri (NorCAS, 2021)

Design Space Exploration of SABER in 65nm ASIC. - Malik Imran; Felipe Almeida; Jaan Raik; Andrea Basso 002; Sujoy Sinha Roy; Samuel Pagliarini (IACR Cryptol. ePrint Arch., 2021)

Systematic Review of Fault Tolerant Techniques in Underwater Sensor Networks. - Lauri Vihman; Maarja Kruusmaa; Jaan Raik (Sensors, 2021)

IMMizer: An Innovative Cost-Effective Method for Minimizing Assertion Sets. - Mohammad Reza Heidari Iman; Jaan Raik; Gert Jervan; Tara Ghasempouri (DSD, 2022)

High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. - Adeboye Stephen Oyeniran; Maksim Jenihhin; Jaan Raik; Raimund Ubar (ISVLSI, 2022)

An Efficient Analog Convolutional Neural Network Hardware Accelerator Enabled by a Novel Memoryless Architecture for Insect-Sized Robots. - Iman Dadras; Mohammad Hasan Ahmadilivani; Saoni Banerji; Jaan Raik; Alvo Aabloo (MOCAST, 2022)

Ransomware Attack as Hardware Trojan: A Feasibility and Demonstration Study. - Felipe Almeida; Malik Imran; Jaan Raik; Samuel Pagliarini (IEEE Access, 2022)

Enhancing Fault Resilience of QNNs by Selective Neuron Splitting. - Mohammad Hasan Ahmadilivani; Mahdi Taheri; Jaan Raik; Masoud Daneshtalab; Maksim Jenihhin (AICAS, 2023)

APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. - Mahdi Taheri; Mohammad Hasan Ahmadilivani; Maksim Jenihhin; Masoud Daneshtalab; Jaan Raik (DDECS, 2023)

Analysis and Improvement of Resilience for Long Short-Term Memory Neural Networks. - Mohammad Hasan Ahmadilivani; Jaan Raik; Masoud Daneshtalab; Alar Kuusik (DFT, 2023)

DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs' Reliability Assessment. - Mohammad Hasan Ahmadilivani; Mahdi Taheri; Jaan Raik; Masoud Daneshtalab; Maksim Jenihhin (ETS, 2023)

Adaptive Kalman Filter Based Data Aggregation in Fault-Resilient Underwater Sensor Networks. - Lauri Vihman; Jaan Raik (DSP, 2023)

Fully-Fusible Convolutional Neural Networks for End-to-End Fused Architecture with FPGA Implementation. - Iman Dadras; Sakineh Seydi; Mohammad Hasan Ahmadilivani; Jaan Raik; Mostafa E. Salehi (ICECS, 2023)

ML-Based Online Design Error Localization for RISC-V Implementations. - Hardi Selg; Maksim Jenihhin; Peeter Ellervee; Jaan Raik (IOLTS, 2023)

DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. - Mahdi Taheri; Mohammad Riazati; Mohammad Hasan Ahmadilivani; Maksim Jenihhin; Masoud Daneshtalab; Jaan Raik; Mikael Sjödin; Björn Lisper (ISQED, 2023)

Special Session: Approximation and Fault Resiliency of DNN Accelerators. - Mohammad Hasan Ahmadilivani; Mario Barbareschi; Salvatore Barone; Alberto Bosio; Masoud Daneshtalab; Salvatore Della Torca; Gabriele Gavarini; Maksim Jenihhin; Jaan Raik; Annachiara Ruospo; Ernesto Sánchez 001; Mahdi Taheri (VTS, 2023)

An automated method for mining high-quality assertion sets. - Mohammad Reza Heidari Iman; Jaan Raik; Maksim Jenihhin; Gert Jervan; Tara Ghasempouri (Microprocess. Microsystems, 2023)

Hybrid Protection of Digital FIR Filters. - Levent Aksoy; Quang-Linh Nguyen; Felipe Almeida; Jaan Raik; Marie-Lise Flottes; Sophie Dupuis; Samuel Pagliarini (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Structural Decision Diagrams in Digital Test - Theory and Applications - Raimund Ubar; Jaan Raik; Maksim Jenihhin; Artur Jutman (Springer, 2024)

ADAssure: Debugging Methodology for Autonomous Driving Control Algorithms. - Andrew Roberts; Mohammad Reza Heidari Iman; Mauro Bellone; Tara Ghasempouri; Jaan Raik; Olaf Maennel; Mohammad Hamad; Sebastian Steinhorst (DATE, 2024)

SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. - Mahdi Taheri; Masoud Daneshtalab; Jaan Raik; Maksim Jenihhin; Salvatore Pappalardo; Paul Jiménez; Bastien Deveautour; Alberto Bosio (DDECS, 2024)

Zero-Memory-Overhead Clipping-Based Fault Tolerance for LSTM Deep Neural Networks. - Bahram Parchekani; Samira Nazari; Mohammad Hasan Ahmadilivani; Ali Azarpeyvand; Jaan Raik; Tara Ghasempouri; Masoud Daneshtalab (DFT, 2024)

Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs. - Hardi Selg; Konstantin Shibin; Anton Tsertov; Maksim Jenihhin; Peeter Ellervee; Jaan Raik (DFT, 2024)

AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. - Mahdi Taheri; Natalia Cherezova; Samira Nazari; Ahsan Rafiq; Ali Azarpeyvand; Tara Ghasempouri; Masoud Daneshtalab; Jaan Raik; Maksim Jenihhin (ETS, 2024)

Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning. - Mohammad Hasan Ahmadilivani; Seyedhamidreza Mousavi; Jaan Raik; Masoud Daneshtalab; Maksim Jenihhin (IOLTS, 2024)

Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators. - Mahdi Taheri; Natalia Cherezova; Mohammad Saeed Ansari; Maksim Jenihhin; Ali Mahani 001; Masoud Daneshtalab; Jaan Raik (ISQED, 2024)

Keynote: Cost-Efficient Reliability for Edge-AI Chips. - Maksim Jenihhin; Mahdi Taheri; Natalia Cherezova; Mohammad Hasan Ahmadilivani; Hardi Selg; Artur Jutman; Konstantin Shibin; Anton Tsertov; Sergei Devadze; Rama Mounika Kodamanchili; Ahsan Rafiq; Jaan Raik; et al. (LATS, 2024)

Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability. - Natalia Cherezova; Salvatore Pappalardo; Mahdi Taheri; Mohammad Hasan Ahmadilivani; Bastien Deveautour; Alberto Bosio; Jaan Raik; Maksim Jenihhin (VLSI-SoC, 2024)

Special Session: Reliability Assessment Recipes for DNN Accelerators. - Mohammad Hasan Ahmadilivani; Alberto Bosio; Bastien Deveautour; Fernando Fernandes dos Santos; Juan-David Guerrero-Balaguera; Maksim Jenihhin; Angeliki Kritikakou; Robert Limas Sierra; Salvatore Pappalardo; Jaan Raik; Josie E. Rodriguez Condia; Matteo Sonza Reorda; et al. (VTS, 2024)

ProAct: Progressive Training for Hybrid Clipped Activation Function to Enhance Resilience of DNNs. - Seyedhamidreza Mousavi; Mohammad Hasan Ahmadilivani; Jaan Raik; Maksim Jenihhin; Masoud Daneshtalab (CoRR, 2024)

DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Network. - Mohammad Hasan Ahmadilivani; Jaan Raik; Masoud Daneshtalab; Maksim Jenihhin (CoRR, 2024)

Survey on Architectural Attacks: A Unified Classification and Attack Model. - Tara Ghasempouri; Jaan Raik; Cezar Reinbrecht; Said Hamdioui; Mottaqiallah Taouil (ACM Comput. Surv., 2024)

A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks. - Mohammad Hasan Ahmadilivani; Mahdi Taheri; Jaan Raik; Masoud Daneshtalab; Maksim Jenihhin (ACM Comput. Surv., 2024)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)

SynAssert: Automated Synthesis of CSCA Leakage Patterns into Cost-Effective Security Assertions. - Ali Azarpeyvand; Mohammad Eslami; Gert Jervan; Jaan Raik; Tara Ghasempouri (ISVLSI, 2025)