A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. - José G. Delgado-Frias; Jabulani Nyathi; Chester L. Miller; Douglas H. Summerville (Great Lakes Symposium on VLSI, 1996)

A VLSI High-Performance Encoder with Priority Lookahead. - José G. Delgado-Frias; Jabulani Nyathi (Great Lakes Symposium on VLSI, 1998)

A wave-pipelined router architecture using ternary associative memory. - José G. Delgado-Frias; Jabulani Nyathi; Laxmi N. Bhuyan (ACM Great Lakes Symposium on VLSI, 2000)

A wave-pipelined CMOS associate router for communication switches. - José G. Delgado-Frias; Jabulani Nyathi (ISCAS, 2000)

A High Performance, Low Area Overhead Carry Lookahead Adder. - James Levy; Jabulani Nyathi (ESA/VLSI, 2004)

A Distributed FIFO Scheme for System on Chip Inter-Component Communication. - Ray Robert Rydberg III; Jabulani Nyathi; José G. Delgado-Frias (ESA/VLSI, 2004)

A charge recycling differential noise immune perceptron. - Jabulani Nyathi; Valeriu Beiu; Suryanarayana Tatapudi; David J. Betowski (IJCNN, 2004)

On the Advantages of Serial Architectures for Low-Power Reliable Computations. - Valeriu Beiu; Snorre Aunet; Jabulani Nyathi; Ray Robert Rydberg III; Asbjørn Djupdal (ASAP, 2005)

A distributed FIFO scheme for on chip communication. - Ray Robert Rydberg III; Jabulani Nyathi; José G. Delgado-Frias (ISCAS (2), 2005)

Decoupled dynamic ternary content addressable memories. - José G. Delgado-Frias; Jabulani Nyathi; Suryanarayana Tatapudi (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Femto Joule Switching for Nano Electronics. - Valeriu Beiu; Jabulani Nyathi; Snorre Aunet; Mawahib H. Sulieman (AICCSA, 2006)

An Efficient Key Update Scheme For Wireless Sensor Networks. - Kamini Prajapati; Jabulani Nyathi (ICWN, 2006)

Logic circuits operating in subthreshold voltages. - Jabulani Nyathi; Brent Bero (ISLPED, 2006)

Evaluation of CPU Utilization Under a Hardware-software Partitioned Enviroment (Migrating Software to Hardware). - Hsiang-Ling Jamie Lin; Jabulani Nyathi; Clint Cole (ESA, 2007)

Multiple clock domain synchronization for network on chip architectures. - Jabulani Nyathi; Souradip Sarkar; Partha Pratim Pande (SoCC, 2007)

Serial Addition: Locally Connected Architectures. - Valeriu Beiu; Snorre Aunet; Jabulani Nyathi; Ray Robert Rydberg III; Walid Ibrahim (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Slowing the none-critical path to improve carry look-ahead adder power dissipation. - Jabulani Nyathi; Abubaker Mutumba (MWSCAS, 2017)

An experimental justification for the proportionality between the coherence bandwidth and the root mean square time delay spread using deterministic time of arrivals. - Saqer Alhloul; Uri Rogers; Donald C. Richter; Jabulani Nyathi (Phys. Commun., 2021)