Logic design verification via test generation. - Magdy S. Abadir; Jack Ferguson; Tom E. Kirkland (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

The Parallel-Test-Detect Fault Simulation Algorithm. - Bill Underwood; Jack Ferguson (ITC, 1989)

An improved layout verification algorithm (LAVA). - Magdy S. Abadir; Jack Ferguson (EURO-DAC, 1990)

Finding I/O Faults on In-Circuit ICs Using Parasitic Transistor Tests. - Jack Ferguson (ITC, 1995)

High Fault Coverage of In-Circuit IC Pin Faults with a Vectorless Test Technique Using Parasitic Transistors. - Jack Ferguson (ITC, 1996)

Capability Maturity ModelingSM at the SEI. - Mike Konrad; Mary Beth Chrissis; Jack Ferguson; Suzanne Garcia; Bill Hefley; Dave Kitson; Mark C. Paulk (Softw. Process. Improv. Pract., 1996)

Flying probe test systems: capabilities for effective testing. - Jack Ferguson (ITC, 1998)

Crouching Dragon, Hidden Software: Software in DOD Weapon Systems. - Jack Ferguson (IEEE Softw., 2001)