A 9.95 to 11.1Gb/s XFP transceiver in 0.13µm CMOS. - Jack Kenney; Declan Dalton; Murat Hayri Eskiyerli; Eric Evans; Barry Hilton; Dave Hitchcox; Terence Kwok; Daniel Mulcahy; Chris McQuilkin; Viswabharath Reddy; Siva Selvanayagam; Paul Shepherd; et al. (ISSCC, 2006)

A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery. - Jack Kenney; Terry Chen; Larry DeVito; Declan Dalton; Stuart McCracken; Richard Soenneker; Ward S. Titus; Todd S. Weigandt (CICC, 2014)

EP3: Innovating on the tapeout treadmill. - Jack Kenney; Frank O'Mahony (ISSCC, 2015)

A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. - Dongwook Kim; Woo-Seok Choi; Ahmed Elkholy; Jack Kenney; Pavan Kumar Hanumolu (CICC, 2018)

A 3-12.5 Gb/s Reference-Less CDR for an Eye-Opening Monitor. - Bob Schell; Robert Bishop; Jack Kenney (ESSCIRC, 2018)

Deep Learning Regression of VLSI Plasma Etch Metrology. - Jack Kenney; John Valcore; Scott Riggs; Edward A. Rietman (CoRR, 2019)

A 15-Gb/s Sub-Baud-Rate Digital CDR. - Dongwook Kim; Woo-Seok Choi; Ahmed Elkholy; Jack Kenney; Pavan Kumar Hanumolu (IEEE J. Solid State Circuits, 2019)

Measuring Interventional Robustness in Reinforcement Learning. - Katherine Avery; Jack Kenney; Pracheta Amaranath; Erica Cai; David D. Jensen (CoRR, 2022)

24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET. - Junhua Shen; Wei-Hung Chen; Efram Burlingame; Stephen Weinreich; Michael Elliott; Stuart McCracken; Jack Kenney; Janet Brunsilius; Anil Korkmaz; Enrique Alvarez-Fontecilla; Nevena Rakuljic; Ushma Mehta; et al. (ISSCC, 2025)