An Sram-Based Accelerator for Solving Partial Differential Equations. - Thomas Chen 003; Jacob Botimer; Teyuh Chou; Zhengya Zhang (CICC, 2019)

CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm. - Teyuh Chou; Wei Tang 010; Jacob Botimer; Zhengya Zhang (MICRO, 2019)

A 1.87-mm2 56.9-GOPS Accelerator for Solving Partial Differential Equations. - Thomas Chen 003; Jacob Botimer; Teyuh Chou; Zhengya Zhang (IEEE J. Solid State Circuits, 2020)

A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer. - Chester Liu; Jacob Botimer; Zhengya Zhang (CICC, 2021)

Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (VLSI Technology and Circuits, 2023)

Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (IEEE J. Solid State Circuits, 2024)