Power-Efficient Fast Write and Hidden Refresh of ReRAM Using an ADC-Based Sense Amplifier. - Sang-Yun Kim; Jong-Min Baek; Dong-Jin Seo; Jae-Koo Park; Jung-Hoon Chun; Kee-Won Kwon (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices. - Hye-Jung Kwon; Eunsung Seo; ChangYong Lee; Young-Hun Seo; Gong-Heum Han; Hye-Ran Kim; Jong-Ho Lee; Min-Su Jang; Sung-Geun Do; Seung-Hyun Cho; Jae-Koo Park; Su-Yeon Doo; et al. (ISSCC, 2017)

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Yoon-Joo Eom; Young-Sik Kim; Min-Su Ahn; Yong-Hun Kim; Sang-Hoon Jung; Sung-Geun Do; Chang-Yong Lee; Jae-Sung Kim; Dong-Seok Kang; et al. (ISSCC, 2018)

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Min-Su Ahn; Yong-Hun Kim; Yong Jae Lee; Dong-Seok Kang; Sung-Geun Do; Chang-Yong Lee; Gun-hee Cho; Jae-Koo Park; Jae-Sung Kim; et al. (IEEE J. Solid State Circuits, 2019)

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM. - Yong-Hun Kim; Hyung-Jin Kim; Jaemin Choi; Min-Su Ahn; Dongkeon Lee; Seung-Hyun Cho; Dong-Yeon Park; Young-Jae Park; Min-Soo Jang; Yong-Jun Kim; Jinyong Choi; Sung-Woo Yoon; et al. (ISSCC, 2021)

A 80Gb/s/pin Single-Ended PAM-4 Transmitter With an Edge Boosting Auxiliary Driver and a 4-Tap FFE in 28-nm CMOS. - Daewon Rho; Jae-Koo Park; Seung-Jae Yang; Woo-Young Choi (A-SSCC, 2023)

Invited paper: Si Photonic Ring-Resonator-Based WDM Transceivers. - Woo-Young Choi; Dae-Won Rho; Jae-Koo Park; Seung-Jae Yang; Jae-Ho Lee; Yongjin Ji (ASP-DAC, 2025)

An 88-Gb/s/pin Single-Ended PAM-4 Transmitter in 28-nm CMOS With Duty-Cycle-Error and Quadrature-Phase-Error Correction Using Pre-Coded Data Patterns. - Jae-Koo Park; Dae-Won Rho; Woo-Young Choi (NewCAS, 2025)

A 4λ× 50-Gb/s Si Photonic WDM Transmitter with Code-Based Wavelength Calibration and Locking. - Dae-Won Rho; Jae-Koo Park; Yongjin Ji; Seung-Jae Yang; Woo-Young Choi (OFC, 2025)

An 80-Gb/s/pin Single-Ended Voltage-Mode PAM-4 Transmitter With a Pulsewidth Pre-Emphasis and a 4-Tap FFE in 28-nm CMOS. - Jae-Koo Park; Dae-Won Rho; Seung-Jae Yang; Woo-Young Choi (IEEE J. Solid State Circuits, 2025)