An antifuse EPROM circuitry scheme for field-programmable repair in DRAM. - Jae-Kyung Wee; Woodward Yang; Eui-Kyu Ryou; Joe-Sun Choi; Seung-Han Ahn; Jin-Yong Chung; Sea-Chung Kim (IEEE J. Solid State Circuits, 2000)

Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier. - Sanghoon Hong; Sejun Kim; Jae-Kyung Wee; Seongsoo Lee (IEEE J. Solid State Circuits, 2002)

A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM. - Se Jun Kim; Sang Hoon Hong; Jae-Kyung Wee; Joo-Hwan Cho; Pil Soo Lee; Jin-Hong Ahn; Jin-Yong Chung (IEEE J. Solid State Circuits, 2002)

A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs. - Jae-Kyung Wee; Kyeong-Sik Min; Jong-Tai Park; Sang-Pil Lee; Young-Hee Kim; Tae-Heum Yang; Jong-Doo Joo; Jin-Yong Chung (IEEE J. Solid State Circuits, 2002)

Low power motion estimator architecture with leakage power reduction in deep sub-micron SoC. - Gyu-Sung Yeon; Chi-Hun Jun; Tae-Jin Hwang; Seongsoo Lee; Jae-Kyung Wee (Circuits, Signals, and Systems, 2004)

Pipelined Bidirectional Bus Architecture for Embedded Multimedia SoCs. - Gang-Hoon Seo; Won-Yong Jung; Seongsoo Lee; Jae-Kyung Wee (EUC, 2005)

Low-Power 32bit×32bit Multiplier Design with Pipelined Block-Wise Shutdown. - Yong-Ju Jang; Yoan Shin; Min-Cheol Hong; Jae-Kyung Wee; Seongsoo Lee (HiPC, 2005)

Low-Power MPEG-4 Motion Estimator Design for Deep Sub-Micron Multimedia SoC. - Gyu-Sung Yeon; Chi-Hun Jun; Tae-Jin Hwang; Seongsoo Lee; Jae-Kyung Wee (KES (3), 2005)

Low-Hardware-Cost Motion Estimation with Large Search Range for VLSI Multimedia Processors. - Seongsoo Lee; Min-Cheol Hong; Jae-Kyung Wee (IEICE Trans. Inf. Syst., 2005)

Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards. - Yong-Ju Kim; Won-Young Jung; Jae-Kyung Wee (IEICE Trans. Electron., 2006)

A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips. - Ji-Hoon Lim; Jong-Chan Ha; Won-Young Jung; Yong-Ju Kim; Jae-Kyung Wee (IEICE Trans. Electron., 2007)

Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches. - Won-Young Jung; Hyungon Kim; Yong-Ju Kim; Jae-Kyung Wee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Seamless-Controlled Digital PLL Using Dual Loops for High Speed SoCs. - Young San Shin; Jae-Kyung Wee; Jong-Chan Ha; Ji-Hoon Lim; Yong-Ju Kim; Young-Sang Son (J. Circuits Syst. Comput., 2011)

Current readout circuit using two-stage amplification method for 64-channel CNT arrays. - Young San Shin; Seongsoo Lee; Jae-Kyung Wee (ISCAS, 2012)

One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique. - Young-Kyun Park; Ji-Hoon Lim; Jae-Kyung Wee; Inchae Song (ISOCC, 2012)

A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique. - Ji-Hoon Lim; Won-Young Jung; Yong-Ju Kim; Inchae Song; Jae-Kyung Wee (IEICE Trans. Electron., 2013)