Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis. - Jae-Seok Yang; Jeong-Yeol Kim; Joon-Ho Choi; Moon-Hyun Yoo; Jeong-Taek Kong (ISQED, 2003)

Overlay aware interconnect and timing variation modeling for double patterning technology. - Jae-Seok Yang; David Z. Pan (ICCAD, 2008)

Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner. - Jae-Seok Yang; Andrew R. Neureuther (ISQED, 2008)

A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. - Jae-Seok Yang; Katrina Lu; Minsik Cho; Kun Yuan 002; David Z. Pan (ASP-DAC, 2010)

TSV stress aware timing analysis with applications to 3D-IC layout optimization. - Jae-Seok Yang; Krit Athikulwongse; Young-Joon Lee; Sung Kyu Lim; David Z. Pan (DAC, 2010)

Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. - Krit Athikulwongse; Ashutosh Chakraborty; Jae-Seok Yang; David Z. Pan; Sung Kyu Lim (ICCAD, 2010)

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization. - Kun Yuan 002; Jae-Seok Yang; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. - Jae-Seok Yang; Jiwoo Pak; Xin Zhao 001; Sung Kyu Lim; David Z. Pan (ASP-DAC, 2011)

Layout aware line-edge roughness modeling and poly optimization for leakage minimization. - Yongchan Ban; Jae-Seok Yang (DAC, 2011)

Chemical-mechanical polishing aware application-specific 3D NoC design. - Wooyoung Jang; Ou He; Jae-Seok Yang; David Z. Pan (ICCAD, 2011)

Design for manufacturability and reliability for TSV-based 3D ICs. - David Z. Pan; Sung Kyu Lim; Krit Athikulwongse; Moongon Jung; Joydeep Mitra; Jiwoo Pak; Mohit Pathak; Jae-Seok Yang (ASP-DAC, 2012)

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). - Bei Yu 001; Jhih-Rong Gao; Duo Ding; Yongchan Ban; Jae-Seok Yang; Kun Yuan 002; Minsik Cho; David Z. Pan (ICCAD, 2012)

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs. - Krit Athikulwongse; Jae-Seok Yang; David Z. Pan; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)